Dolphin Integration releases an innovative test solution for embedded memories

Meylan, France – November 05, 2010 -- Dolphin Integration announces the HD BIST as a complement of its High Density - Low Power Panoply of silicon IP.

"Because of the trend to increase design complexity so as to offer more features to their end customers - while maintaining competitive pricing, the requirements for scattered memories in today’s SoCs are increasing", said Elsa BERNARD-MOULIN, Product Manager, Dolphin Integration Memory Product Line: "a typical SoC contains hundreds of memory instances making memory testing a major challenge for the SoC architects in terms of routing congestion and of the associated area penalty of the Built-In Self Test circuitry (BIST) as well as concerns such as power-consumption and difficulty to perform at-speed testing of multiple memory instances. On the other hand, non-optimized BIST implementations would penalize TTM, manufacturing costs and product reliability. Dolphin Integration is pleased to announce an innovative customer-aware testing solution, the HD-BIST".

The HD BIST is a breakthrough solution which can be used for helping SoC designers to embed memory BIST in their design at the lowest silicon cost:

• The HD BIST is 50% smaller than alternative test solutions!
• Innovative architecture for a reduced routing overhead

The HD BIST can be used for helping test engineers to reduce the Time-to-market:

• Quick fault detection thanks to parallel testing of several instances
• True “Self-Test” resulting in a pass/fail indication
• BIST solution optimized per instance

The HD BIST is a flexible test solution for ensuring high memory reliability:

• Algorithm programmability
• Test under actual conditions of use (frequency, voltage…)
• To diagnose yield loss and define the appropriate corrective actions, the HD-BIST can be combined with Dolphin Integration’s BISD (Built-In Self Diagnostic)

Please follow the link below to get access to the key benefits and features of the HD BIST

http://www.design-reuse.com/sip/view.php?id=24845

The HD BIST is part of the High Density – Low Power Panoply including:

• Single Port and Dual Port Memory Arrays
• One-Port and Two-Port Memory Register Files
• Metal Programmable ROM
• High Density and High Speed Standard Cell Library

For more information about the High Density – Low Power Panoply:

http://www.design-reuse.com/sip/view.php?id=23771

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control.

For more information about Dolphin, visit: www.dolphin.fr/ragtime

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