MoSys 1T-SRAM Macros Now Proven in Multiple Versions of TSMC'S Standard and Triple-Oxide 0.13-Micron Logic Processes
MoSys 1T-SRAM Macros Now Proven in Multiple Versions of TSMC'S Standard and Triple-Oxide 0.13-Micron Logic Processes
SUNNYVALE, Calif. & HSINCHU, Taiwan--(BUSINESS WIRE)--Nov. 12, 2001--MoSys (Nasdaq:MOSY - news) and Taiwan Semiconductor Manufacturing Company (TSM) today announced that MoSys 1T-SRAM® technology has now been verified on multiple versions of TSMC's 0.13-micron standard and triple-oxide logic processes with excellent yield results. TSMC is now ready to accept customers' tapeouts utilizing these 0.13-micron triple-oxide logic processes. MoSys and TSMC further announced verification and excellent test and yield results of 1T-SRAM test memory cells targeted for the 0.10-micron process generation. MoSys is already in the process of implementing 1T-SRAM memory macros fully adjusted for TSMC's 0.10-micron optimized logic process.
"As designers move increasingly to system-on-chip methodologies, we see growing customer interest in easily manufacturable embedded high-density memories," said Genda Hu, vice president of marketing at TSMC. "TSMC has consistently been the first foundry to successfully manufacture 1T-SRAM in mass production and has a strong alliance with MoSys. Starting with 0.13um generation, we are committed to providing a logic process especially optimized for 1T-SRAM."
Mark-Eric Jones, MoSys' vice president and general manager of intellectual property commented, "Our close collaboration with TSMC over the last two years in porting and verification of our 1T-SRAM embedded memory macros over five generations of standard logic processes had been extremely successful and productive. Both TSMC and its customers benefit greatly from the dramatic cost savings and time-to-volume advantages delivered by our embedded 1T-SRAM technology. We will continue our collaboration with TSMC on their most advanced logic processes to provide mutual customers with the best and most complete 1T-SRAM offering at the earliest stage."
About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, seven eight-inch fabs and two six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 0.10-micron technology alignment program with its customers. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC please go to http://www.tsmc.com.
About MoSys
Founded in 1991, MoSys develops, licenses and markets innovative memory technology for semiconductors. MoSys' patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM technology results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic manufacturing processes. 1T-SRAM technology also offers the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it an ideal technology for embedding large memories in System on Chip (SoC) designs. 1T-SRAM technology is in volume production both in SoC products at MoSys' licensees as well as in MoSys' standalone memories. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, CA 94085. More information is available on MoSys' website at http://www.mosys.com.
Note to Editors: 1T-SRAM®is a MoSys trademark registered in the U.S. Patent and Trademark Office. All other trademarks or registered trademarks are the property of their respective owners.
Contact:
MoSys, Sunnyvale
Kathleen T. Boyle, 408/731-1830
kboyle@mosys.com
or
TSMC North America, San Jose
Dan Holden, 408/382-8000
dholden@tsmc.com
Related News
- MoSys' 1T-SRAM Memory Silicon-Verified on DongbuAnam's 0.18-Micron Standard Logic Process; 0.13-Micron Verifications Initiated
- TSMC implements MoSys' new low-power 1T-SRAM for 0.13-micron process
- MoSys' 1T-SRAM(R) CLASSIC Running in Volume Production on Chartered's 0.13-micron Process
- MoSys' 1T-SRAM-Q Memory Silicon-Verified on Chartered's 0.13-Micron Industry Standard Logic Process
- MoSys' Ultra-High Reliability 1T-SRAM-R Technology Verified on SMIC 0.13-Micron Logic Process
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |