PCI-SIG Releases PCI Express 3.0 Specification
PCIe 3.0 specification doubles bandwidth over previous generations
BEAVERTON, Ore. -- November 19, 2010 -- PCI-SIG®, the organization responsible for the widely adopted PCI Express® (PCIe®) industry-standard input/output (I/O) technology, today announced the availability of the PCIe Base 3.0 specification to its members. The PCIe 3.0 architecture is a low-cost, high-performance I/O technology that includes a new 128b/130b encoding scheme and a data rate of 8 gigatransfers per second (GT/s), doubling the interconnect bandwidth over the PCIe 2.0 specification. PCIe 3.0 technology also maintains backward compatibility with previous PCIe architectures and provides the optimum design point for high-volume platform I/O implementations across a wide range of topologies. Possible topologies include servers, workstations, desktop and mobile personal computers, embedded systems, peripheral devices and more.
“Each new version of the PCIe spec has doubled the bandwidth of the prior generation,” said Nathan Brookwood, research fellow at Insight 64. “The latest group of PCIe architects and designers drove the standard forward while maintaining complete backward compatibility for Gen 1 and Gen 2 devices. Rarely has a standard advanced so non-disruptively through three major evolutionary cycles. The ability to pull this off demonstrates not only the ingenuity of the Gen 3 developers, but also the insight of those who defined the earlier versions in such an extensible manner.”
The PCIe 3.0 specification extends the data rate to 8 GT/s in a manner compatible with the existing PCIe 1.x and 2.x specifications and products that support 2.5 and 5 GT/s signaling. This bit rate represents the most optimum tradeoff between manufacturability, cost, power, complexity and compatibility. Based on this data rate expansion, it is possible for products designed to the PCIe 3.0 architecture to achieve bandwidth near 1 gigabyte per second (GB/s) in one direction on a single-lane (x1) configuration and scale to an aggregate approaching 32 GB/s on a sixteen-lane (x16) configuration. The new 128b/130b encoding scheme also allows near 100% efficiency, offering a 25% efficiency increase for 8 GT/s as compared to the 8b/10b efficiency of previous versions, which enables the doubled bandwidth.
“The PCI-SIG remains dedicated to I/O innovation and we are proud to release the PCIe 3.0 specification to our members,” said Al Yanes, PCI-SIG chairman and president. “The PCIe 3.0 architecture details significant improvements over our two previous PCIe specifications, providing our members with the performance and functionality they need to continue to be innovators in their fields.”
This evolutionary specification integrates a number of enhancements to the protocol and software layers of the architecture. These enhancements range in scope from data reuse hints, atomic operations, dynamic power adjustment mechanisms, latency tolerance reporting, loose transaction ordering, I/O page faults, BAR resizing and many more extensions in support of platform energy efficiency, software model flexibility and architectural scalability.
The PCIe Base 3.0 specification is available for member download at http://www.pcisig.com/specifications/pciexpress/base3/.
Benefits of PCI-SIG Membership
There are many valuable PCI-SIG membership benefits including the right to receive patent licenses from any other member of the organization, with necessary claims of patent embodied within the PCI-SIG specifications. These licenses may be limited in scope to an implementation of a particular specification, but must be granted to all members on reasonable and non-discriminatory terms.
PCI-SIG members can also participate in the review of all PCI specifications before they are released to the industry, gain access to interoperability testing at Compliance Workshops, participate in PCI-SIG activities such as developer conferences, and receive Vendor ID assignments. PCI-SIG members develop and maintain PCI Express specifications and are actively involved in defining compliance criteria and other technical enabling collateral. To join, visit the PCI-SIG website at www.pcisig.com/membership.
About PCI-SIG
PCI-SIG is the Special Interest Group that owns and manages PCI specifications as open industry standards. The organization defines and implements new industry standard I/O (Input/Output) specifications as the industry’s local I/O needs evolve. The PCI Special Interest Group was formed in 1992 and became a nonprofit corporation, named “PCI-SIG,” in the year 2000. Currently, more than 900 industry-leading companies are active PCI-SIG members worldwide. PCI-SIG’s current directors are employed by the following PCI-SIG member companies: Agilent, AMD, Dell, HP, IBM, Intel, LSI, NVIDIA and Oracle. For more information about the PCI-SIG and its membership benefits, please visit the PCI-SIG Web site at http://www.pcisig.com or contact 503-619-0569 (within the United States).
|
Related News
- Northwest Logic's PCI Express 3.0 Solution passes PCI-SIG PCIe 3.0 Compliance Testing at First Official PCIe 3.0 Compliance Workshop
- Cadence Demonstrates PCI Express 3.0 Offering at 2011 PCI-SIG Developers Conference
- Gennum Debuts PCI Express 3.0 IP, Showcases Bridging Solutions for HD Video at PCI-SIG
- PCI-SIG Announces PCI Express 3.0 Bit Rate for Products in 2010 and Beyond
- Mobiveil's GPEX PCI Express 3.0 IP Passes PCI-SIG PCIe 3.0 Compliance Testing
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |