Evolution of design methodology II: The re-aggregation era

Paul McLellan
EETimes (12/20/2010 7:17 PM EST)

Editor's note: This is the second of a two part opinion piece authored by EDA luminaries Jim Hogan and Paul McLellan. The first installment was posted Nov. 24.

Unlike previous changes to the abstraction level of design, the block level not only goes down into the implementation flow, but also goes up into the software development flow. Software and chip-design must be verified against each other. Since the purpose of the chip is to run the software load, it can't really be optimized any other way.

There is, today, no fully-automated flow from the block level all the way into implementation. A typical chip will involve blocks of synthesizable IP typically in Verilog, VHDL or SystemVerilog along with appropriate scripts to create efficient implementations. Other blocks are designed at a higher level, or, perhaps pulled from the software for more efficient implementation. These blocks are in C, C++ or SystemC. The key technology here is high-level synthesis (HLS). This provides the capability to reduce system behavioral models to SoC almost automatically.

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