Avery Design Systems Enhances USB Solution for xHCI and UASP

ANDOVER, Mass.-- January 24, 2011 --Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced updates to the USB-Xactor verification solution supporting the xHCI 1.0 and USB Mass Storage Class protocols for USB Serial Attached SCSI (UASP) and Bulk Only Transfer (BOT).

USB-Xactor is a complete verification solution consisting of SystemVerilog OVM/VMM compliant host, device, and hub models, protocol checkers, directed and random compliance test suites, and reference verification frameworks. The USB-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their designs incorporating USB host, hub, device, and PHY designs for SuperSpeed, High-Speed, Full-Speed operation. Core-level verification of USB controllers and PIPE PHY cores and full SoC-level verification is fully supported.

“USB-Xactor provides a comprehensive verification solution for many semiconductor companies and more than four USB IP vendors,” said Chris Browy, vice president of sales and marketing of Avery Design Systems. “Our robust models and compliance solution enables designers to thoroughly verify their designs for the USB2, SuperSpeed, and PIPE standards and effectively pinpoint areas of non-compliance.”

Key Features

• xHC Driver model implements the register-level host controller interface for Universal Serial Bus (USB2) Revision 2.0 and USB 3.0. The SystemVerilog VIP emulates the xHC driver that provides the hardware/software interface between system software and the host controller hardware. A xHC compliance testsuite is also supported.
• The xHC driver VIP interfaces with xHC host controllers via various local bus interfaces through Avery’s PCIe and AMBA VIP.
• A mass storage class Host implements the USB Attached SCSI protocol (UASP) and Bulk-Only Transport (BOT) protocols and supports the SCSI and task management commands found under the SPC, SBC, RBC, and SAM standards.
• Generic Host model performs bus enumeration and allocates independent USB pipes for communication flows between host and each device endpoint.
• The storage Host determines whether the USB target device supports UAS or BOT and sequences the SCSI commands accordingly. The storage Host also supports coverage monitors for USB throughput, SCSI command and pipe status.
• The mass storage class testsuite performs SCSI command compliance, performance, and power state verification.

Key BFM Features

• Layered environment based on family of SystemVerilog classes and methods
• Abstract data model for transfer, packet, and descriptor types
• Drivers, event callbacks, and scoreboard options automate status and result checking
• Robust error injection at all layers
• Random scenario generation with constraints stress design operation
• Directed tests for focused functional compliance testing
• Functional coverage monitoring of scenario cases
• Comprehensive protocol checking
• VMM, OVM supported, UVM planned

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of symbolic simulation and formal analysis for bug hunting and coverage closure, robust core-through-chip-level Verification IP for PCI Express, SATA, and USB standards, and scalable distributed parallel logic simulation. The company delivers software products to leading edge semiconductor and systems companies worldwide. Avery Design Systems is privately held. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with GDA Technologies, Snowbush, and Northwest Logic. Avery is a member of the PCI-SIG and USB Implementers Forum. More information about the company may be found at www.avery-design.com.

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