CEVA and Arteris Partner on Multi-Core Interconnect for Next Generation SoC Designs
Arteris joins CEVAnet partner program; CEVA licenses Arteris’ FlexNoC Interconnect IP
SUNNYVALE, California – March 1, 2011 – Arteris Inc., the leading supplier of network-on-chip (NoC) interconnect IP solutions and CEVA, Inc., [(Nasdaq: CEVA); (LSE: CVA)], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today announced that Arteris has joined the CEVAnet partner program, bringing multi-core interconnect expertise to the comprehensive third-party technology offerings for CEVA DSP cores. In addition, CEVA has licensed Arteris’ advanced FlexNoC interconnect IP for optimizing CEVA’s future multi-core platforms.
For many years, CEVA’s industry-leading DSPs have been widely deployed in both homogenous and heterogeneous multi-core SoC architectures for a range of end markets. Next-generation designs call for even greater levels of performance at the lowest power consumption achievable, significantly increasing the challenges for the interconnect architecture and its scalability. To address these challenges, the companies have collaborated to bring Arteris’ advanced FlexNoC interconnect IP together with CEVA’s industry-leading DSP cores in a highly-optimized, high performance multi-core solution.
“Arteris FlexNoC interconnect IP enables higher bandwidth and lower power consumption in multi-core architecture platforms,” said Eran Briman, vice president of marketing at CEVA. “We are pleased to welcome Arteris into our CEVAnet partner program and look forward to helping mutual customers targeting multi-core SoC designs.”
“We are pleased to partner with CEVA and expand the reach of our FlexNoC interconnect IP to address CEVA’s extensive customer base developing multi-core SoCs,” said Charlie Janac, President and CEO of Arteris. “We believe the performance benefits that can be achieved through our partnership will enhance CEVA’s industry-leading products targeted for use in multi-core platforms. This opens a new market segment for Arteris FlexNoC technology as the interconnect of choice for IP providers.”
About Arteris
Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs.
Founded by networking experts and offering the first commercially available Network-on-Chip IP products, Arteris operates globally with headquarters in San Jose, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.
About CEVA, Inc.
CEVA is the world’s leading licensor of silicon intellectual property (SIP) DSP Cores and platform solutions for the mobile handset, portable and consumer electronics markets. CEVA’s IP portfolio includes comprehensive technologies for cellular baseband (2G / 3G / 4G), multimedia, HD video and audio, voice over packet (VoP), Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2010, CEVA's IP was shipped in over 600 million devices, powering handsets from 7 out of the top 8 handset OEMs, including Nokia, Samsung, LG, Motorola, Sony Ericsson and ZTE. Today, more than one in every three handsets shipped worldwide is powered by a CEVA DSP core. For more information, visit www.ceva-dsp.com.
|
Ceva, Inc. Hot IP
Related News
- Mentor Graphics Questa Verification Platform Adds Software-Driven Verification for Multi-Core SoC Designs
- Arteris Adds Support for Tensilica’s Dataplane Processor Core Interface, Expanding Multi-core SOC Network-on-Chip Options
- CoWare and ARM Partner to Enable Rapid Configuration of AMBA NIC-301 Network Interconnect-based SoC Designs in SystemC
- 3DSP and CoWare Partner to Strengthen Design Processes and High-Level Verification for Multi-Core DSP SoC Solutions
- Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |