CAST IP and Aldec Simulators Unite for Smoother FPGA and ASIC Design Flow

Woodcliff Lake, NJ, March 7, 2011 — Semiconductor intellectual property (IP) provider CAST, Inc. and electronic design automation (EDA) firm Aldec, Inc. have partnered to ensure that CAST’s IP cores are compatible with Aldec’s suite of design verification tools.

This means that ASIC and FPGA designers using Aldec’s Riviera-PRO™ or Active-HDL™ simulators with CAST’s IP cores can count on a smooth design and verification experience. CAST is also now a member of Aldec’s Unite IP partner program.

“From high-quality products through complete product deliverables to comprehensive support and integration services, we do all we can to give CAST customers a better IP experience,” said Nikos Zervas, Vice President of Marketing for CAST. “Our partnership with Aldec continues this effort, and designers seeking superb verification tools or great IP products will both benefit.”

Aldec’s Active-HDL™ and Riviera-PRO™ HDL simulators offer a complete FPGA or ASIC verification environment, including effective design creation, and high-performance RTL and gate-level simulation. They use a high-speed, mixed-language simulation engine that supports VHDL, Verilog®, SystemVerilog and SystemC/C/C++. They also feature optimal waveform toolsets, ultra-fast debugging tools, code coverage and a set of advanced verification methods. Learn more about Aldec’s simulators and additional products at www.aldec.com.

“CAST’s reputation as an excellent IP provider makes them a good match for designers in Aldec’s growing customer base,” said Christina Toole, Marketing Manager for Aldec, Inc. “We’re pleased to recommend CAST’s IP products through our Unite IP Partner Program.”

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