English
DeFacTo Technologies Announces PLX Technology Adopts HiDFT-SIGNOFF Solution for RTL Testability
Grenoble, France, March 9, 2011. DeFacTo Technologies S.A. today announced that PLX Technology has adopted DeFacTo Technologies’ HiDFT-SIGNOFF Design for Test solution. PLX’s portfolio of high-end PCIe Switches, PCIe Bridges, NAS and DAS storage solutions, USB Controllers and other connectivity products will all benefit from increased test coverage earlier in the design flow, without requiring additional engineering resources.
“As process geometries shrink, the importance of robust DFT and high coverage becomes critical given the increase in gate count and chip complexity,” said Vijay Meduri, vice president of engineering, PLX. “At 40nm nodes and below, there are significantly more steps in the signoff flow which leave very little room for errors to be found late in the flow. With the deployment of the DeFacTo solution we are now able to prevent any last minute surprises in the DFT implementation.”
“We are excited about our collaboration with PLX. Their designs showcase the capabilities of HiDFT-SIGNOFF, especially when it comes to complex control and communication logic where our distinctive capabilities will help PLX engineers reach high-level testability figures in a fraction of the time”, said Chouki Aktouf, Founder & CEO of DeFacTo Technologies. Mr. Aktouf added, “PLX should now see lower NRE and testing costs for the development and production of every design, which uses SIGNOFF in their DFT flow.”
About DeFacTo Technologies
DeFacTo Technologies is a leading provider of Design-for-Test solutions at RTL. DeFacTo solutions enable designers to achieve “Design & DFT” closure at RTL by delivering a high quality suite of tools, which cover planning, analysis, insertion and debug needs. DeFacTo EDA tools HiDFT-SIGNOFF and HiDFT-STAR are silicon proven and are being used by major semiconductor companies to increase fault coverage predictability by strengthening Design and DFT quality at RTL and also by eliminating communication gap between DFT engineers and RTL designers. DeFacTo is headquartered at 167 rue de Mayoussard, 38430 Moirans, France. For more information, visit us at www.defactotech.com.
|
||||||
Related News
- Ricoh Adopts DeFacTo HiDFT-SIGNOFF Solution for Digital IC Design for Test
- Socionext Adopts Defacto Solution for RTL and Gate-level Design Analysis and Building
- DeFacTo Demonstrates to TESSOLVE the Effectiveness of its RTL Testability Sign-off Solution
- Defacto Announces STAR 8.0 and Provides a Unified "All-in-One" SoC Design Solution to Help Conciliating Between RTL, IP-XACT, UPF, SDC, and Physical Design Information
- Defacto Technologies Announces Synapse Design in collaboration with a major semiconductor company Reduces Simulation Time by 5X When using Defacto's RTL Design Solutions
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |