Update: Quake prompts supply chain worries
Mark LaPedus , Peter Clarke, EETimes
3/11/2011 11:29 AM EST
LONDON – It is still hard to find out the state of a number of wafer fabs in the prefectures closest to the massive earthquake, and resulting tsunami that hit Japan Friday (March 11).
Normally factories, which are built to withstand earthquakes in the area, suffer little damage and the worst that happens is a loss of work in progress. However, the magnitude of the quake--which measured 8.9 on the Richter scale--may have been significant enough to damage factories. Re-establishing electricity and water supplies and transportation links may take many days.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
- Apple-TSMC-Amkor Pact Bolsters U.S. Chip Supply Chain
- proteanTecs Collaborates with BAE Systems to Enable a Zero Trust Supply Chain for Defense Applications
- ShortLink AB joins X-FAB's Design & Supply Chain Partner Network and IP Portal
- Supply Chain Experts Weigh In on CHIPS Act
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset