DATE 2011: SoC realization, the elephant in the room
James Hogan, EETimes
3/17/2011 4:50 AM EDT
There was an interesting panel discussion at this week’s Design Automation and Test in Europe (DATE) Conference that included representatives from various links in the SoC supply chain – EDA suppliers, IP providers, services companies and even a bona fide SoC developer. The panelists were asked to provide their view of where the EDA and IP industries were headed. Like the proverbial blind men who are asked to describe what is in front of them by touching different parts of an elephant, everyone brought a slightly different perspective to the table.
But not as different as you might think. Interestingly, five of the six panelists focused the majority of their talk on IP. For good reason: IP, and more generally design reuse, is the crux of SoC’s future and value proposition. Everyone agrees that the ability to quickly and efficiently re-use silicon-proven functionality in new designs holds the key to addressing the technical complexity, time pressures and jaw-dropping economics of bringing new SoCs to market. There simply is no other way.
E-mail This Article | Printer-Friendly Page |
Related News
- Cadence Appoints Martin Lund to Lead SoC Realization Group
- DAC 2011: How to Respond to the ITRS SoC Design Cost Slide
- Cadence Accelerates SoC Realization, Reduces Costs With New Open Integration Platform
- Legend and Circuit Semantics Invite EDA Community to Demos at DATE That Show How to Improve Timing and Characterization of SoC Designs
- Date 2002 conference to spotlight IP, SoC issues
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards