Intilop announces a record breaking Ultra low latency & highest bandwidth 10G bit TCP offload engine SOC for Altera FPGA family

The Mega_IP_SOC integrates 10G TOE, 10G EMAC, DDRx, ARM CPU, Scalable Streaming FIFO interface. Also provides 256+ TCP sessions depending upon the FPGA size and still keeps the latency in the 100 ns range.

Santa Clara, CA – March 21, 2011 - Intilop Inc., a leading developer and provider of advanced high complexity IPs and system solutions in Network protocol processing, traffic acceleration, traffic management and network security, today announced a Mega_IP_SoC for Altera FPGAs that integrates their much heralded flagship 10G bit TCP Offload Engine, their own very low latency 10G EMAC, AMBA APB CPU controller, DDR-2 or DDR-3 controller, mdio controller. It also extends the TOEs capability of providing 256 and more concurrent TCP sessions, depending upon FPGA size. They accomplished this feat without compromising highest throughput and ultra low latency in the industry. The latency of ~100 ns was made possible by patent pending advanced dynamic array search architecture.

In addition optional features in TOE_SoC are; a variety of CPU interface, UDP Offload (optional), PCIe Gen-3.  This 10G TOE reduces CPU’s involvement in TCP processing by more than 95%, presents a very attractive solution to the latency sensitive financial markets and is a critical building block for the current and future high performance networking equipment in converged IP networks.  It is targeted towards Altera GXIII/IV/V FPGA families and can also be targeted to Xilinx and other FPGA families. Further details are available upon request.

Due to its flexible architecture, the developers of high end FPGAs/ASICs/ASSPs, Network adapters, Lan-on-Mother board (LOM) and very large scale FPGA-SoC IP integrators can provide differentiated solutions to the end users in financial markets, web servers, email servers, high end servers in Data centers, Government network systems, university network systems. The 10G TOE is intilop’s 3rd generation flagship TOE architecture, based upon their industry-proven 1 G TOE architecture. The highly flexible and scalable architecture offers customers, ability to customize it to suite their specific application. This is the only TCP offload engine that is also scalable and is easily customizable to suit different types of network traffic.

The highly integrated, highly scalable full Offload TOE employs patent pending high performance VLIW microcode machines and advanced search hardware design techniques that test the limits in FPGA and ASIC design/integration technologies. It employs best of cut-through and store-and-forward architectural features that utilize intilop’s third generation TOE, EMAC and DMA designs. There are so many features that are easily configurable which make the value proposition even more useful and powerful. The unprecedented customizable features as options include; scalable number of TCP sessions, multiple (2-4) 10G Ethernet MACs, VLAN support, TCP Bypass mode, Fiber Channel over Ethernet (FCoE) support and others.

"We responded to our existing TOE customer’s requests to deliver a series of TOE engines with least latency and highest bandwidth possible that are also customizable. Having a fixed architecture does not provide the capability to deliver differentiated solutions. We hope that with this type of scalability, flexibility and performance, Intilop’s 10G TOE really opens up tremendous opportunities for next generation of hyper performance advanced system solutions in IP networks”, said K Masood, President and CTO.

Intilop Corporation is a developer and pioneer in advanced networking silicon IP and solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and engineering services provider for Networking, Network Security, storage and Embedded Systems. They offer silicon proven semiconductor IP and solutions with comprehensive hardware and software development experience

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