Startup rolls suite of cores, tools for DSP subsystems
Startup rolls suite of cores, tools for DSP subsystems
By Patrick Mannion, EE Times
February 26, 2002 (9:53 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020226S0008
MANHASSET, N.Y. Intellectual-property core vendor Adelante Technologies will serve up a soup-to-nuts suite of digital-signal-processing cores at the Embedded Systems Conference next week. The company's DSP Galaxic will include intellectual property (IP), subsystems and tools for the development of complete DSP subsystems for multiprocessor systems-on-chip. Galaxic, which bundles a raft of well-known concepts and proven DSP technology, will initially target wireless baseband processing and control applications. Although Adelante (Leuven, Belgium) is launching its products in an unfavorable IP startup climate, it is banking on the comprehensiveness and reconfigurability of its suite and the low-power, high-performance capabilities of the DSP core at the heart of its architecture. Adelante's position as a small spin-off from a big company brings its own p roblems, however. The company was formed from the merger last year of Philips' DSP group and Frontier Design. While the expertise and funding at its disposal have not been questioned, those same advantages could prove to be the company's undoing, according to Jeff Bier, general manager of Berkeley Design Technologies Inc. (Berkeley, Calif.). "Being a spin-off of Philips leaves [Adelante] with some baggage," he said. "It's a big step from being part of a massive corporation like Philips to being part of a small operation that must sink or swim based on its own merits." And although Frontier, which began life as a spin-off from Mentor Graphics, had experience in that mode, Bier added, it's like switching from a supertanker to a rowboat. "The captains must recognize that it's a fundamentally different paradigm," he said. Bier is strong on the Galaxic concept in general, however. "As a whole package, I'm not familiar with any other vendor that has pulled all this together." The method has merit, he said. "Adelante has a lot of advantages with a mature technology, a seasoned team and a lot of financial backing. They're years ahead in terms of development for a startup." While there have been many core startups over the last few years, few have been successful to date, "and a number have disappeared or shifted their business models," Bier said. Lexra Inc. is a case in point. The company is no longer seeking to license its family of MIPS-compatible cores, and is now a fabless chip company concentrating on network processors. "The wave has crested, and you might say Adelante is late to a party that's breaking up, but they're bringing some assets and capabilities that the others don't have. It's actually fairly mature technology, and it's more comprehensive than the basic core the others offer," Bier said. Will Strauss, president of Forward Concepts, said a startup without Adelante's pedigree "would take upwards of $100 million to get to their capabilities. Also, they 've already got a customer in Philips, which supplies revenues through hard times." Adelante's Galaxic comes armed with several families of extensible DSP cores. The newest entry is the 210-MHz, dual-Harvard Saturn with a die area of 0.5 mm2 and power consumption of 0.25 milliwatts per MHz. The first register-transfer-level DSP core from Adelante, it is functionally similar to all other Galaxic cores in that it is reconfigurable. That feature allows designers to expand the core's standard 16-bit instruction set by creating an additional 256, 96-bit VLIW application-specific instructions, said Mark Bloemendaal, director of marketing at Adelante. These application-specific instructions, he said, use all the core's resources in parallel and can execute as many as 12 operations in a single clock cycle. Saturn's data path resources are also extendible, he said. Augmenting the core The core comes supplied with 16- and 32-bit instructions that have been optimi zed for the execution of wireless, speech and digital-control functions. These allow, for example, a 256-point fast Fourier transform (FFT) to be executed in 3,100 clock cycles. The core can be augmented at a number of other levels. The first is through application-specific hardware execution units (AXUs), which typically add fewer than 1,000 additional gates to the core, according to the company. Adelante develops and verifies the AXUs, integrates them into the Saturn core and verifies the entire subsystem for the customer. The level of subsystem integration provided by Galaxic is one of its strong points, Bloemendaal said. Bier noted the usefulness of the AXU verification and subsystem integration approach. "As chip designs become more and more complex, the designers don't want to be assembling small components; they want to buy complete subsystems and put them together, much like the automotive industry." That approach does have some risks, however. "As you integrate more and more into the subsystem, you may not end up delivering exactly what the customer wants," Bier said. In addition, "This might also be inconvenient or impractical, as customers might have IP issues and Adelante engineers might be backlogged," and hence unable to meet time-to-market demands. Coprocessors in hand "At the next level [out from the AXUs]," Bloemendaal said, "we also supply application-specific coprocessors that are integrated into the Lunar DSP subsystem and are tightly linked to the core." (Lunar is the trademark name for the general DSP subsystem, which includes all the DSPs.) The company already has Viterbi, 802.11a baseband, complex FFT and turbo-coding coprocessors in hand. The Galaxic architecture is supported by what Adelante calls its Atmosphere Development Environment, which provides both code development and debugging support for the application-specific instructions and AXUs. Mentor Graphics' Seamless Co-verification environment and a debugger based on Ment or's XRay technology may be used for the simultaneous co-verification of the core with its software. The Atmosphere Development Environment will be formally announced in June at the Design Automation Conference in New Orleans. Other Galaxic features include on-chip JTAG emulation and run-time debug support, and field-programmable gate array prototyping support for Xilinx Virtex FPGAs. Future cores will expand from the 16-bit Saturn into a 24-bit DSP as well as another 16-bit DSP. Galaxic is available now. According to Strauss, Adelante's solution will appeal to either sophisticated system vendors that want to design their own silicon, or chip houses that need a new product in their portfolio in the general-purpose DSP market. "In many senses, Tality and Parthus would be the only real competition [for Adelante]," he said. Strauss sees a lot of companies showing interest in having their whole design come from one place.
Related News
- Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs
- Xilinx Vivado Design Suite 2015.3 Takes Design to New Heights with IP Sub-Systems
- KYOCERA Document Solutions Uses Synopsys' Application-Specific Instruction-Set Processor Tool to Accelerate Design of High-Performance Image Processing DSP
- Authorized As the Distributor of ARM Keil Tools, Faraday Provides the Complete Family of ARM Development Tools
- Thalia Design Automation Ltd completes A round funding and prepares to launch suite of Analog and Power design optimisation tools
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |