English
3-D ICs stack up design challenges
Ron Wilson, EETimes
4/20/2011 11:24 AM EDT
In an address to the GlobalPress Forum in Santa Cruz on March 29, Mentor Graphics Chairman and CEO Walden Rhines (See picture) outlined the likely evolutionary stages of 3-D IC development, from today's relatively simple stacked dice to a distant future of design in a homogeneous 3-D space. Along that path Rhines identified several points of interest.
To start at the beginning, the first patent on through-silicon via (TSV) technology, Rhines said, was granted to transistor pioneer William Shockley in 1958. From there, the idea of moving signals from the top to the bottom surface of a die by drilling a hole straight through languished until recently, when TSVs became the most popular candidate for moving signals between layers of a 3-D IC.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Chip execs see 20 nm variants, 3-D ICs ahead
- 3-D Stacking Reaches New Heights : Tachyon Semiconductor Creates Four-Wafer Stack
- Latest Release of Lattice sensAI Solutions Stack Delivers up to 6X Performance Boost on Award-Winning CrossLink-NX FPGAs
- New Cadence Clarity 3D Transient Solver Delivers Up to 10X Faster System-Level EMI Simulation
- GLOBALFOUNDRIES and Arm Demonstrate High-Density 3D Stack Test Chip for High Performance Compute Applications
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models