Accellera Announces IP Tagging Effort, Calls for Participation
IP Tagging Tracks Soft IP Throughout the Design and Development Process and Benefits Semiconductor Foundries, IP Providers and Electronic Design Tool Providers
NAPA, CA--Apr 27, 2011 -- Accellera, the electronics industry organization focused on the creation and adoption of Electronic Design Automation (EDA) standards and Intellectual Property (IP) standards, announced today that it is kicking off an IP Tagging effort that will benefit the electronics industry by tracking soft IP information which will be automatically added and detectable in the final GDSII database format. Accellera is also calling for participation in its IP Tagging Technical Subcommittee (TSC) efforts. Interested parties are invited to join and participate.
Soft IP, particularly from third party vendors, must be tracked to satisfy contractual obligations such as royalty reporting and usage. Control of the third party IP source is lost once IP is licensed, unlocked or otherwise made available in clear code. Accellera's IP Tagging TSC will develop a standard and methodology to utilize tags in soft IP that are readable in GDSII databases.
"Our Soft IP Tagging effort has a rich history and is an effort that is of real benefit to the electronics and semiconductor industry stakeholders," noted Shishpal Rawat, Accellera chair. "This effort began with the VSI Alliance and was passed on to the SPIRIT Consortium, and it is now under Accellera due to our merger with the SPIRIT Consortium."
"We are looking forward to kicking off our efforts and defining milestones that will help us realize a working specification in 2012," added Kathy Werner, Accellera's IP Tagging Technical TSC chair.
What the Industry Is Saying
"My perspective in regard to IP tagging always has been less focused on piracy and more on royalty audits," said Jim Hogan, Private Investor. "To have an effective and fair way to audit IP usage enables a predictable business model. This in turn allows companies to have a common approach to enterprise valuations. The opportunity with the Accellera effort will establish a standard and consistent way of applying an IP tag. This lowers everyone's cost and resistance to adoption on the buy and sell side of the IP equation. Tastes great and has no calories. A win-win."
"The electronics industry needs a soft IP Tagging standard to protect and secure its investments," remarked Richard Wawrzyniak, Sr. Market Analyst at Semico Research Corp. "Tracking the version of the IP would do more than add security through such a standard; it would alert IP consumers if there are compatibility issues. Given Accellera's history of developing IP-XACT and the hardware description languages for developing soft IP, it is the best organization to develop this standard."
"The IP world is desperately in need of standards that simplify IP reuse," added Gary Smith, Chief Analyst, Gary Smith EDA. "Accellera is taking on the challenge. This tagging standard is a good step in the right direction."
More about IP Tagging
An IP Tagging standard provides a way to track IP information as it passes throughout the design and development process. The design process can include editing, synthesis, timing, placement, wiring, and other steps leading to GDSII generation. Semiconductor foundries, providers of IP blocks, and design tool providers can use the methods described by an IP tagging standard to track identification information throughout each level of the development process and more specifically, in the final GDSII database. Because tags are intended to be readable on the text layer of the GDS format, previous IP Tagging implementations have been specific to cells and hard IP. Text tags instantiated in soft IP have not been recognized or carried forward by traditional EDA tools and are therefore not currently available in the GDSII database to verify actual implementation and usage. How to Join Accellera's IP Tagging TSC
To join the IP Tagging TSC, please visit www.accellera.org to sign up.
About Accellera
Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA and IP standards that lower the cost to design commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.
|
Related News
- Accellera Approves Verilog-AMS 2023 Standard for Release
- Accellera Announces IEEE 1666™-2023 Standard Available Through IEEE GET Program
- Credo Joins with Industry Players to Announce Effort to Standardize CXL Active Electrical Cables & Optics at OCP Global Summit 2023
- Accellera Releases Portable Test and Stimulus Standard 2.1
- Arasan furthers the compliance of their I3C IP with its participation in the I3C Interop at MIPI Member Meeting
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |