TransEDA Launches Industry's First IP Quality Alliance Program
IP Vendors Join with Verification Leader to Provide Customers with Objective Proof of Quality for IP Cores
Los Gatos, Calif. (USA) - March 4, 2002 - TransEDA® PLC, the leader in ready-to-use verification solutions for electronic systems, announced the launch of the TransEDA IP Quality Alliance Program, through which silicon IP vendors can provide their customers with an independent and objective measurement of how well their IP cores have been verified.
The program offers an online service to provide IP users with objective and detailed evidence of the quality of an IP core's verification. In addition, the program provides member companies with a complimentary copy of TransEDA's VN-Property DX[tm] dynamic property checker to facilitate development of IP properties to help their customers speed verification of IP-based designs.
"There has already been a lot of interest in the TransEDA IP Quality Alliance Program, and we believe it will deliver competitive advantages to both IP providers and their customers," said Udo Muerle, vice president of European sales at TransEDA. "Through the program our IP vendors can differentiate themselves from other IP companies by offering potential customers an independent assessment of how well their IP cores have been verified. In addition, prospective IP customers can more easily justify their investment in IP cores, and purchase with more confidence than ever before."
Founding Members
Founding members of the TransEDA IP Quality Alliance Program include Evatronix S.A., Fraunhofer IMS, Memec Inicore AG (Memec Design Services), Mentor Graphics, sci-worx and Tality.
"Through its contributions to both the Reuse Methodology Manual and OpenMORE, Mentor Graphics has been instrumental in defining and using a high-quality verification process for IP cores," said Jimmy Awan, director of engineering for the Mentor Graphics Inventra IP Division. "We have used TransEDA's verification products for many years to assess and improve our verification process. We welcome the IP Quality Alliance as a way we can provide evidence of the quality of our cores to our valued customers."
Peter Neumann, senior engineer for system-on-chip integration at sci-worx said, "sci-worx is dedicated to providing the highest quality, best-verified IP. We verify all of our cores to 100% statement, 100% branch and 90% condition coverage and look forward to providing objective evidence of this to our customers through TransEDA's IP Quality Alliance program. In addition, we are eager to begin working with TransEDA to provide property libraries that our customers can use to speed the verification of systems incorporating our cores."
The Need For Quality Assurance
The use of third-party IP cores alongside in-house generated blocks to build system-on-chips (SoCs) is commonplace, but selecting 'off-the-shelf' IP cores can be difficult since quality varies widely. There is no way to know if a core has been fully verified. With rising development and production costs, IP consumers need to be confident they can integrate third-party IP with their design with minimal risk of delay due to integration or debug issues.
According to Muerle, "TransEDA has identified a real need of IP users for a method of objectively qualifying silicon intellectual property. IP providers typically do not supply evidence of the verification quality of their IP cores, and there is no recognised criterion for measuring the quality, so consumers are left with a difficult choice."
How the Program Works
The IP Quality Alliance Program procedure is easy to use, automated and free of charge for members and their customers. Program members provide the results files from TransEDA's VN-Cover[tm] coverage analysis solution and VN-Check[tm] configurable HDL checker to their prospective customer. After a short registration process on the TransEDA web site, the prospective customer uploads the results files to the program's web site at www.transeda.com/ipquality.
The prospective customer can then view an objective report on the level of coverage achieved by the IP vendor's verification process and the IP core?s conformance to specific HDL rules. This independent view of the level of verification quality can be used as a comparison metric between similar cores from different vendors.
In addition, members can use TransEDA's VN-Property DX dynamic property checker to better verify their IP and to develop core-specific properties that can be delivered along with each IP core. This will enable IP customers using VN-Property DX to measure how well they have verified the core once it has been integrated in the system.
Joining the TransEDA IP Quality Alliance Program
IP vendors who are interested in joining the TransEDA IP Quality Alliance Program should e-mail ipquality@transeda.com for more information.
Qualified IP vendors who join the program in 2002 will receive a complimentary, one-year subscription license to TransEDA's VN-Property DX dynamic property checker so they can begin developing properties specific to their IP cores. These properties can be delivered to customers along with a core to accelerate verification of the core when it is integrated into a system. Additional details and requirements for the program can be obtained at the program?s website at www.transeda.com/ipquality.
Contacts:
TransEDA - Tom Borgstrom,
(408) 907-2225; tom.borgstrom@transeda.com.
PentaCom - Sharon Graves,
+44 1242 525205, sharon.graves@btinternet.com.
Armstrong Kendall, Inc.
- Jen Bernier, (408) 975-9863, jen@akipr.com.
Related News
- VESA Launches Industry's First Open Standard and Logo Program for PC Monitor and Laptop Display Variable Refresh Rate Performance for Gaming and Media Playback
- Siemens joins Intel Foundry Services' EDA Alliance program
- Omnitek's video IP-cores prove a hit with Xilinx customers
- Chips&Media Joins TSMC's Soft-IP Alliance Program
- Sonics Joins TSMC's Soft IP Alliance Program
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
E-mail This Article | Printer-Friendly Page |