Digital Blocks Expands the DB9000 TFT LCD Controller IP Core Family with Support for the AMBA AXI4 Interconnect
Taking advantage of the AXI4 QoS and long burst length capabilities, the DB9000AXI4 targets High Resolution TFT LCD panels applications.
GLEN ROCK, New Jersey, May 10, 2011 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with Embedded Processor & Peripherals, Networking, Display Controller, Display Link Layer, 2D Graphics, and Audio / Video processing requirements, today announces the DB9000AXI4 TFT LCD Controller IP Core. The DB9000AXI4 IP Core extends Digital Blocks 3 years of experience with the AXI protocol, with the AXI4 QoS and long bursts lengths, supporting high resolution LCD panels.
While the DB9000AXI4 targets high resolution TFT LCD panels, the range of programming parameters permit support for a wide range of LCD panel resolutions. Representative examples are as follows:
Format | Resolution |
Square | 240 x 240 |
QVGA | 240 x 320 |
240 x 400 | |
320 x 240 | |
16:9 Aspect Ratio | 480 x 234 |
480 x 272 | |
VGA | 480 x 640 |
640 x 480 | |
WVGA | 480 x 800 |
800 x 480 | |
SVGA | 800 x 600 |
960x540 | 960 x 540 |
WSVGA | 1024 x 576 |
1024 x 600 | |
XGA | 1024 x768 |
SXGA | 1280 x 1024 |
HD / WXGA | 1366 x 768 |
WXGA+ | 1440 x 900 |
HD+ | 1600 x 900 |
UXGA | 1600 x 1200 |
WSXGA+ | 1680 x 1050 |
Full HD | 1920 x 1080 |
WUXGA | 1920 x 1200 |
DCI 2K | 2048 x 1080 |
3M pixels | 2048 x 1536 |
CSHD | 2560 x 1080 |
5M pixels | 2560 x 2048 |
8M pixels | 3840 x 2160 |
DCI 4K | 4096 x 2160 |
10M pixels | 4096 x 2560 |
DB9000 Family of TFT LCD Controllers
The DB9000 family of TFT LCD Controllers supports a variety of bus interfaces to frame buffer memory and processors. Please consult Digital Blocks web site for a complete listing.
Price and Availability
The DB9000AXI4 is available immediately in synthesizable Verilog, along with a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please go to Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; Fax: +1-201-632-4809; Media Contact: info@digitalblocks.com; Sales Inquiries: info@digitalblock.com; On the Web at www.digitalblocks.com
|
Digital Blocks Hot IP
Related News
- Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AXI for the AMBA 3.0 Interconnect
- Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AHB for the AMBA 2.0 Interconnect
- Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with Support for Quad Full High Definition (QFHD) LCD Panels
- Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000OCP for the Open Core Protocol 2.2 Interconnect
- Digital Blocks DB9000 TFT LCD Display Controller IP Core Family Achieves Leadership Across Medical, Industrial, Aerospace, Automotive, Communications, Computer, Monitor, Consumer, IoT, Wearables, and Cinema Applications
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |