Design tools prepped for systems-on-programmable-chips

Design tools prepped for systems-on-programmable-chips
By Michael Santarini, EE Times
March 5, 2002 (10:16 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020304S0061

SAN MATEO, Calif. — As the major programmable-logic vendors introduce large, complex system-on-programmable-chip devices, some top-tier EDA vendors are scrambling to tailor their ASIC tool flows for the budding SoPC market.

At the Design Automation and Test in Europe conference here this week, Mentor Graphics Corp. will introduce the Precision Synthesis Platform, which combines an SoPC design cockpit and Mentor's latest revision of the Exemplar Leonardo FPGA synthesis technology with a built-in timing analysis engine based on Mentor's SST Velocity ASIC static-timing analyzer. The platform is the first deliverable from Mentor's Project Atlanta initiative, through which Mentor plans to field a complete tool flow for SoPC devices over the course of the next year.

Meanwhile, Synopsys Inc., whose bread and butter has been the ASIC tool market, is moving forward with ef forts to ensure that its ASIC tools can be used in the SoPC flow and that its FPGA Compiler II FPGA synthesis technology is ready for immediate use as SoPC devices are introduced by vendors such as Xilinx Inc. and Altera Corp.

The moves come as Xilinx, in releasing the Virtex-II Pro FPGA with embedded PowerPC processors, has created a tool set that will allow embedded engineers to do hardware/software partitioning and then let the tool automatically generate most of the hardware and software components.

Mike Bohm, chief scientist at Mentor Graphics, said the new Precision Synthesis platform is still in the beta phase but is due out later this quarter. It targets users of the Stratix and Excalibur architectures from Altera and the new Virtex-II Pro Platform FPGAs, but it can also be used for FPGAs and complex PLDs.

When FPGA vendors announced the SoPC concept a couple of years ago, Mentor chairman and chief executive officer Wally Rhines showed high interest in pursuing the devices as a potentially high-growth market, hinting that Mentor would tailor many of its ASIC technologies to the new opportunity.

Synopsys also considers SoPC a growth market, and it is working with FPGA vendors to ensure that its FPGA Compiler II synthesis, dynamic and formal verification tools can be used by high-end ASIC and SoPC designers, said Jackie Patterson, director of marketing programs for RTL synthesis at the EDA company. Synopsys owns market share in many points of the ASIC tool flow, and the company is confident that its success in the ASIC tool market will translate to SoPC market dominance when SoPC devices require ASIC-strength tools.

Investment tally

Among the top-tier EDA vendors, however, it's Mentor that is making the largest investment in the SoPC market, in a bid to catch up with Cadence and Synopsys in the overall EDA landscape, said Gary Smith, chief EDA analyst with Gartner Dataquest.

"The total involved in SoC design in 2000 was $1.7 billion; the total in embedded design was $1.5 billion; and the total in component-based design was $175 million, $50 million of which was for FPGA design tools," said Smith. "FPGA design tools aren't a huge market; but if you can tap into the embedded design world, which these devices now tend to target, all of a sudden you have a market that is about the size of the SoC market."

If Mentor can field tools in advance of the competition and grab even a small percentage of the embedded-design money, the company "could potentially grow as big as Synopsys and Cadence," Smith said.

Synplicity Inc., too, will likely be able to leverage its dominance in the FPGA synthesis space as more complex devices are introduced, Smith said. But so far Synplicity has been a point tool company specializing in FPGA synthesis and is just now moving to such markets as ASIC prototyping and ASIC synthesis, Smith said. It does not offer the other tools that most industry observers say will be needed to design SoPC devices.

ASIC-strength tools

ASIC vendors previously have not invested heavily in this arena, Smith said, because FPGA designers are accustomed to getting tools at little or no cost from FPGA vendors, which make up for the cost of the tool giveaway by selling mass silicon. But now programmable-logic vendors have created architectures so complex that designing with the parts will require ASIC-strength tools, such as hardware/software co-verification and co-design, simulation, formal verification, signal integrity and timing analysis.

That's what Mentor's Project Atlanta initiative is all about. Bohm said the Precision Synthesis Platform is the first of many ASIC-strength tools Mentor will release under that project. Bohm oversees the project and spent the past year pulling in the appropriate resources from across Mentor's product divisions to create a full ASIC-stren gth tool flow for SoPC products.

The Precision Synthesis Platform contains a design cockpit, called Design Center, that designers use to control a version of Mentor's Leonardo Spectrum FPGA synthesis tool. It also has a static-timing engine from Mentor's ASIC analysis tool, SST Velocity, for a perpetual single-vendor license of $16,000.

Mentor has built an interactive common database and timing engine into Design Center. The Design Center database tracks changes and can be adjusted accordingly, Bohm said.

"The way the browser is set up is that we read the design in, figure out all the clocks and put them in a clock folder," he said. "You can go to the clock folder itself and say, 'Set up clock for 100 MHz,' or you could set up one clock to have a relationship with another clock." The database links tools and lets users alternate between schematic and report file views.

The Precision Synthesis Platform includes an overhaul of the Exemplar Leonardo Spectrum level-3 synthesis tool. "We took th e tech-mapping stuff and a few other things from Leonardo and said, 'How do we make it faster and get a better quality of results?' " Bohm said.

The answer was a new algorithm called Architecture Signature Extraction (ASE). Bohm claims the algorithm provides up to 63 percent better performance on critical paths and a 50 percent performance improvement in finite state machine optimizations compared with synthesis tools. The ASE looks at designs at a high level, identifies major elements and automatically focuses optimization on specific areas that likely hinder overall performance.

Bohm said the algorithm uses an automated, heuristic approach and performs such tasks as lookup table merging, logic tunneling, register retiming and timing-driven I/O block mapping to reach the target performance without the need for iterative manual user intervention.

The company has also integrated its SST Velocity static-timing engine into the Precision Synthesis Platform engine.

Bohm said the timing engine wi ll help the company build on the synthesis technology to create a physical-synthesis offering for SoPC devices.

The company over the next year plans to release a high-level synthesis tool running System C or another system-level language, formal verification, and a link to Mentor's pc-board tool flow, all targeting SoPC designers. Bohm said the high-level synthesis tool, which should be released by the Design Automation Conference this June, is currently in alpha test.