CoWare adds bus synthesis to N2C system
CoWare adds bus synthesis to N2C system
By Nicolas Mokhoff, EE Times
March 7, 2002 (11:04 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020305S0022
PARIS CoWare Inc. has enhanced its N2C design system with what it calls second-generation Interface Synthesis capabilities, which enable automatic synthesis of the bus interconnect matrixes and crossbar switches at the heart of multilayer buses in current system-on-chip designs. Arbitration logic for multiple bus masters, and all other bus logic, is also synthesized by the system.
CoWare said its N2C allows designers to build accurate simulation models for different bus configurations. A designer specifies graphically which bus masters connect to which bus slaves via which node, with each node producing a distinct bus or bus layer. With second-generation Interface Synthesis, N2C removes the guesswork in making such tradeoffs.
CoWare (Santa Clara, Calif.) said its technology allows a designer to mix and match master and slaves of different types and, with the Interface Synthesis technology, synthesize an implementation-specific b us topology based on the proper bus architectures, including decoders, arbiters, and bridges.
This capability has been proven in production designs using ARM Ltd.'s Amba 2.0 bus and STMicroelectronics' STbus, according to Pete Hardee, director of product marketing at CoWare.
"Many of our new SoC designs use the advanced features available in Amba and STbus," said Jean-Marc Chateau, director of Design, Consumer and Microcontroller Groups for STMicroelectronics. "We worked with CoWare to enhance N2C for building platform variants exploiting these advanced features."
Following simulation, N2C's analysis tools let designers check the performance of different configurations. To change from one bus configuration to another, the designer adjusts the high-level input and re-synthesizes.
Once the optimal bus architecture is established, the hardware design can be validated and implemented in an RTL-based design flow, the company said.
CoWare provides ways for a designer to mi x and match different types of blocks. A typical system contains a number of connected hardware blocks, some masters (CPU and DMA, for example) and some slaves (timers and UARTs, for example). These blocks are connected via channels which may be incompatible, with different data types, primitive protocols, or bus protocols.
Most SoCs include a high-performance, high-bandwidth bus for components such as cores and memory controllers, and another bus for lower data-rate peripherals such as serial or parallel ports, UARTs, and timers. The logic used for communicating between the bus structures needs to be configurable, based on the data rate and the number of masters and slaves.
In addition to standard buses such as Amba, STbus, and IBM's CoreConnect, many companies use proprietary buses. Bridges are required not only to join buses of the same type but also to bridge between different bus standards. CoWare's Interface Synthesis enables the synthesis between these different bus structures, the c ompany said.
Related News
- Breker Verification Systems Unveils System Coherency Synthesis TrekApp Building on Its Successful Cache Coherency Test Solution
- Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO's DO-254 Plug-In
- Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis
- INSIDE Secure DRM Fusion Adds Support for Google Widevine Modular DRM System
- Fujitsu Kansai-Chubu Net-Tech Shortens Design Time by 40 Percent on 100G Transport System with Cadence High-Level Synthesis Solution
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |