Bluetooth low energy v5.4 Baseband Controller, Protocol Software Stack and Profiles IP
OCP-IP Delivers Memory Model Package
Beaverton OR. — June 8, 2011 — Open Core Protocol International Partnership (OCPIP) today announced the availability of an Accurate Dynamic Random-Access Memory Model (ADM) package. The ADM is a configurable, transaction-level model for Dynamic Random-Access Memories (DRAMs). This model is more accurate than existing DRAM models currently used for system-simulation because it considers the major delay parameters of real DRAMs and imitates their timing behavior with access dependencies captured. A demonstration program provided in the package can be used to test the delay and throughput of the DRAM for certain traffic flows, more accurately representing the performance of systems and enabling a realistic evaluation of in those systems.
The model package was developed in SystemC using OCP-IP’s TLM Kit, and can be combined with other OCP-compatible modules through an OCP TL1 interface. The OCP TLM kit is the first, and most advanced TLM-2.0 based, industry-ready kit. The TLM Kit significantly increases performance, ease-of-use and ensures alignment with the OSCI 2.0 standard. The kits are free, as part of OCP-IP membership entitlement and save users hundreds of thousands of dollars annually in development, documentation, and training costs otherwise required to develop such kits independently.
This new ADM package was developed by Royal Institute of Technology (KTH) in conjunction with members of OCP-IP’s Network on Chip Benchmarking working group including: Tampere University of Technology, Boston University, University of British Columbia, Carnegie Melon University, Princeton, Washington State University, and Transylvania University in cooperation with industry members of the OCP-IP.
The memory model package was developed based on a white paper on the subject of memory modeling titled, “A Memory Subsystem Model for Evaluating Network-on- Chip Performance.”
The package is freely available to both OCP-IP members and non-members alike, through GNU LGPL licensing at http://www.ocpip.org/memory_model.php.
“The work on this memory model package by our Network on Chip Working Group enables co-operation and collaboration among both industry and academic researchers, ensuring synergy advantages in the field of NoCs,” said Ian Mackintosh, president and chairman of OCP-IP. “We are extremely proud to host our forum where the world’s most prestigious universities and industry researchers in the field of NoC investigation can come together.”
A fully functional version of OCP-IP’s TLM kit without monitors is also available free to non-members, via click through research license agreement from www.ocpip.org. More information on the TLM Kits is available here.
The Network on Chip Benchmarking Working Group has also issued an open call for Benchmarks to be distributed to researchers. NoC researchers may submit benchmarks from any application domain to be included. For more information on the call for benchmarks, please see http://www.ocpip.org/ocpspec_call_for_benchmarks.php
Institutions interested in joining the work of OCP-IP’s Network on Chip Benchmarking Working Group should contact admin@ocpip.org
About OCP-IP
Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.OCPIP.org.
|
Related News
- OCP-IP Delivers Enhanced Transaction Generator Package
- OCP-IP Delivers Enhanced Transaction Generator Package
- OCP-IP Delivers Transaction Generator Package
- Uniquify Delivers High-Performance DDR3 Memory System Running in Low-Cost, Wire Bond Package
- OCP-IP Announces Availability of New Memory Modeling White Paper
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |