Cadence tools to support Xilinx SoPC devices

Cadence has not actively offered tools for FPGAs, said Mike O'Reilly, director of marketing for system and functional verification at Cadence. But many engineers on their own have elected to use Cadence's tools, such as simulation, to aid FPGA designs. But with Xilinx and Altera Corp. releasing production silicon that contains one or more processor cores and a block of programmable logic, Cadence sees a huge opportunity to expand its user base, he said.

Cadence's ASIC tool rivals, Synopsys Inc. and Mentor Graphics Corp., have invested heavily and have a head start on tools for this emerging class of programmable chips.

Previously, FPGA vendors offered their own tool flows to customers at low or no cost as an incentive to buy their silicon. To make it big in FPGA tools, electronic design automation vendors would have had to lower tool prices and hope for volume sales — a gamble that could potentially waste R&D dollars.

Devices like Xilinx's SoPCs boast upward of 1 million gates and are reaching ASIC complexity. To get to the full potential of these devices in terms of performance will likely require ASIC-level design skills and tools.

Pushbutton flows

At the same time, FPGA vendors are busy devising pushbutton flows that they hope will allow embedded-system designers with little knowledge of hardware design to use SoPC-type part s, thus growing the silicon and perhaps the tool markets substantially.

This design complexity has seemingly opened a window for EDA vendors to sell ASIC-strength tools to a new market — FPGA designers and potentially embedded-systems designers — at or near ASIC tool price points.

"This reinvigorated focus on FPGA really comes about as customers move to higher levels of abstraction and are designing pretty big FPGAs with complex cores," said O'Reilly. "As we look at the latest introductions of the Xilinx technology, they are starting to push up into the same issues as we have in ASIC design today." Moreover, he said, "Some of our larger accounts, which have traditionally gone to ASIC design," are contemplating "these more complex and complete offerings" from the FPGA side instead.