English
Averant Adds RTL and Gate Level Combinational Equivalency Checker
HAYWARD, Calif.--August 01, 2011--Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announces the release of Solidify 5.4. Some of the highlights of this release are listed below.
- Combinational Equivalency Checker. When proving two designs are equivalent, a significant portion of the two designs are combinationally equivalent. A fast combinational equivalency checker (CEC) is added to Solidify to catch such cases.
- Improved Sequential Equivalency Checking (SEC). The SEC engines have been enhanced to provide speed-ups of several orders of magnitude in some cases, in addition to improved proving powers.
Release 5.4 also provides better System Verilog Design support, speed-ups in formal engines, improved reset sequence guessing, improved SEC debugging, improved protocol checking including ARM AMBA protocols, and bug fixes.
“Our Japanese customers have always been enthusiastic about Averant’s innovations in formal technologies,” commented Seiichi Nishio, COO of GAIA System Solutions Inc. “I am confident Averant’s leadership in being the first company to combine important and correlated formal technologies in one product will be well-received by our customers.”
Availability
Release 5.4 is available immediately.
About Averant
Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant’s flagship product is Solidify, a robust platform for property, protocol, and automatic design checks – all without the need for simulators or test vectors. Averant’s tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.
|
||||||
Related News
- Averant's Solidify 6.5 Significantly Improves Combinational and Sequential Equivalency Checking and Clock Domain Crossing Checks
- CHERI Alliance Officially Launches, Adds Major Partners including Google, to Tackle Cybersecurity Threats at the Hardware Level
- Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO for DO-254 Projects
- OneSpin Solutions Adds RTL-to-RTL Equivalence Checking to Product Family
- Dialog Semiconductor adds ARM multicore support in next generation of system level power management ICs
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
|
E-mail This Article | 
|
|
Printer-Friendly Page |