USPTO Examiner Maintains Position on Sidense's '855 Patent - Upholding Its Validity Over the Kilopass Peng Patents
Update: Synopsys Expands DesignWare IP Portfolio with Acquisition of Sidense Corporation (Oct. 17, 2017)
USPTO Examiner rejects Kilopass’ arguments on Appeal
Ottawa, Canada - (Sept. 2, 2011) - Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) one-time programmable (OTP) memory IP cores, announced that the United States Patent and Trademark Office (USPTO) Examiner has reasserted his position that all eleven claims in Sidense’s U.S. Patent No. 7,402,855 (‘855) patent are valid over the Kilopass Peng patents, once again rejecting Kilopass’ arguments to the contrary. All ‘855 patent claims remain "confirmed." A copy of the Examiner’s Answer is available on Sidense’s website.
In May of 2010, based on its own Peng patents (the same patents which Kilopass says Sidense is infringing), Kilopass asked the USPTO to invalidate Sidense’s ‘855 patent. The ‘855 patent covers Sidense’s one-transistor one-time programmable (1T-OTP) bit cell – the allegedly infringing product. In January of 2011, after considering Kilopass’ arguments, the USPTO Examiner affirmed validity of the original four claims of the ‘855 patent and granted seven additional claims, bringing the affirmed number of claims on ‘855 up to eleven. Kilopass appealed this decision, making further arguments.
Now, in August of 2011, after considering Kilopass’ further arguments on appeal, the USPTO Examiner has rejected those further arguments, and re-affirmed Sidense’s position.
About Sidense Corp.
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense SiPROM, SLP and ULP memory products, embedded in over 160 customer designs, are available from 180nm down to 40nm and are scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit www.sidense.com.
|
Related News
- USPTO Validates Sidense's Non-infringement Position and Rejects Two Kilopass Patents
- US Patent and Trademark Office (USPTO) Rejects All Claims of Sidense's Key Patent ('855) and Orders Reexamination
- Sidense Defeats Kilopass' Remaining Claims; Kilopass' Case is Over
- Sidense Files Action Against Kilopass Patents at USPTO
- Judge Orders Kilopass to Pay Sidense $5.5 Million in Legal Fees and Costs for Baseless Patent Infringement Lawsuit
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |