Industry-Leading Lattice MachXO2 PLD Family Now Available In Small WLCSP Package
Extremely Small Footprint and Over 100X Power Reduction Highlight Benefits for Low Density PLD Designers
HILLSBORO, OR – SEPTEMBER 6, 2011 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that it is now shipping samples of its MachXO2™ PLD family using a 2.5mmx2.5mm 25-ball Wafer Level Chip Scale Package (WLCSP). The MachXO2 devices now combine an extremely small footprint — until now unprecedented in the PLD market — with the industry's lowest power and most feature rich low density PLDs. Built on a low power 65nm process featuring embedded Flash technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory and more than a 100X reduction in static power compared to previous generations. With the industry's most robust PLD functionality, ultra-low power and new WLCSP packaging, the MachXO2 devices can now address applications previously not accessible to PLDs.
"WLCSP is a superior packaging solution for markets that demand the smallest possible form factor," said Mike Orr, Lattice Vice President of Product Development. "WLCSP features outstanding performance for signal integrity, power management and thermal characteristics. WLCSP is also cost effective, reliable and uses standard board mounting processes for simple handling and manufacturability."
Tiny Footprint Packages a Key Differentiator for the MachXO2 Family
The MachXO2 family leads the industry in providing the lowest power and highest functionality of any PLD family. Now Lattice is extending its lead in the low density PLD market by offering a portfolio of small footprint die/package combinations for the MachXO2 family to be made available throughout 2011, including:
- A 2.5mmx2.5mm 25-ball WLCSP, shipping immediately: Die size-defined BGA with 0.4mm solder ball pitch, providing 19 user I/O in a 6.1mm2 footprint
- A 3.2mmx3.2mm 49-ball WLCSP: Die size-defined BGA with 0.4mm solder ball pitch, providing 40 user I/O in a 9.8mm2 footprint
- A 4mmx4mm 64-ball ucBGA: Saw singulated BGA with 0.4mm solder ball pitch, providing 45 user I/O in a 16.0mm2 footprint
- A 8mmx8mm 132-ball ucBGA: Saw singulated BGA with 0.5mm solder ball pitch, providing up to 105 user I/O in a 64.0mm2 footprint
"We have combined aggressive packaging technologies to deliver some of the smallest PLD footprints ever in the programmable logic industry. When these footprints are combined with the superior functionality and ultra-low power available on the MachXO2 devices, we are able to address a new class of applications not previously available to SRAM-based PLDs," said Shakeel Peera, Director of Marketing for Silicon and Solutions at Lattice Semiconductor. "There is little doubt that consumer device connectivity and space constraints are moving in opposite directions. These new MachXO2 devices will enable new possibilities for digital logic designers focused on these space constrained applications, without having to sacrifice flexibility or programmability."
Pricing and Availability
MachXO2 LCMXO2-1200ZE devices in the 25 WLCSP are now available as engineering samples, with production devices scheduled to be available by Q4 2011. All other ultra-low footprint packages mentioned in this news release will be sampling by the end of 2011. Pricing for the LCMXO2-1200ZE 25WLCSP is $0.95 in 100KU volume. For more information about the Lattice MachXO2 PLD family, visit http://www.latticesemi.com/machxo2/tiny.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
|
Related News
- New Reference Designs Enhance Embedded Function Block Of Lattice MachXO2 PLD Family
- Lattice Announces New 32 QFN Package For MachXO2 Programmable Logic Devices
- Lattice Semiconductor and System General Announce Programming Support for Lattice MachXO2 PLD Family
- Lattice MachXO2 PLD Family Sets New Standards for Low Cost, Low Power Designs
- New Package Option for Lattice MachXO PLD Family Reduces Cost and Board Area
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |