Intel adds third-party IP for 10-Gbit chips in fabless ASIC business

Intel adds third-party IP for 10-Gbit chips in fabless ASIC business
By Mark LaPedus, Semiconductor Business News
March 15, 2002 (2:08 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020315S0055

SANTA CLARA, Calif. -- Aiming to enable a new class of IC designs for communications systems, Intel Corp.'s new fabless ASIC operation today announced a complete set of chip building blocks and intellectual-property (IP) cores for use in 10-gigabit-per-second applications.

The company's fabless ASIC unit--called Intel Microelectronics Services--also announced ASIC library deals with a number of chip, IP, and electronic-design automation (EDA) vendors to enable the development of chip designs for 10-Gbps applications. Intel announced deals with Artisan, Leda Systems, Mentor Graphics Nurlogic, Rambus, Synopsys, and TriCN.

Intel's ASIC unit is focusing on chip designs based on 0.18-to-0.13-micron processes, although it is also taking orders for next-generation 0.09-micron technologies as well, said Naveed Sherwani, general manager of Intel Microelectronics Services, based in Hillsboro, Ore.

Meanwhile, Intel's IP and EDA alliances will help ena ble the development of application specific integrated circuits (ASICs), application specific standard parts (ASSPs), and other chip designs in 10 Gigabit Ethernet and SONET/SDH networks, Sherwani said.

"We have a rich set of building blocks for 10-gigabit-per-second applications," Sherwani said. "We also believe that we have the IP to support 10-gigabit-per-second ASIC designs," he said in an interview with SBN today.

The move expands Intel's new and bold efforts in the fabless ASIC market. In a move that could alter the semiconductor landscape, Intel Corp. last year formally launched a new business that will provide fabless ASIC, global logistics and other services for customers.

Intel Microelectronics Services a new turnkey business model that aims to help develop ASICs, ASSPs and system-on-a-chip designs for IC makers and system houses. In general, the service is geared for the communications space.

The Santa Clara chip giant claims that it will not use its own wafer fabs in this new ASIC service. Instead, Intel's fabless ASIC unit will utilize three major foundries: Singapore's Chartered Semiconductor Manufacturing Pte. Ltd., Taiwan Semiconductor Manufacturing Co. Ltd., and United Microelectronics Corp. in Taiwan (see Sept. 24 story).

While some of the traditional ASIC houses have dismissed Intel's efforts to propel the fabless model, Intel claims that it is experiencing greater-than-expected demand for its new services.

"We are pleasantly surprised," Sherwani said. "Everybody thought that 2001 was going to be weak. But our design capacity is fully utilized right now. Our design capacity is fully utilized through the first quarter [of 2002]. We are now taking orders for Q2 and Q3 [of 2002]," he said.

So far, some 60% of the designs within Intel Microelectronics Services involve the communications market. The bulk of its business also involves ASICs "with two-to-five million gates and 200-MHz clock rates," h e said.

And surprisingly, some 50% of its chip designs are already geared for leading-edge, 0.13-micron technologies. Chip makers are under extreme "pressure to move to 0.13-micron," he said. "We are taping out at r0.13-micron right now," he said.

Intel is also engaging with customers at the 90-nm (0.09-micron) node, but the company does not predict a lot of activity in this arena for some time. "We have customer requirements for 90-nm," he said. "But in general, the ASIC business lags two or three quarters [behind the logic and DRAM markets]," he said.

The company does predict strong demand for ASIC and ASSPs in the communications market in spite of the current and severe downturn in the segment. "Companies [in the communications space] are still working on new designs," said Fred Cohen, director of marketing for Intel Microelectronics Services. "The new design activity has not been impacted by the economic downturn," he told SBN.

In fact, the 10-Gbps ASIC/ASSP market is expected to reach $2.7 billion by 2007, according to Dataquest Inc. of San Jose. Right now, the market is only a "couple of hundred of million dollars," according to Cohen.

To help customers develop their designs in the 10-Gbps space, Intel has forged an assortment of IP and EDA alliances. The company's offerings are sub-divided into three categories: building blocks, core components and standard cells-I/O IP.

In the building block arena, Intel's libraries include various interfaces, such as SPI, SFI, XAUI, and XGMII. It also offers building blocks for serial/deserializer (SerDes) application. It also offers several core components, such as embedded memories, digital signal processors, USB, PCI, and others.