Altera Demonstrates Industry's First Model-Based Floating-Point DSP Capabilities for FPGAs
Altera's New Highly-Efficient Floating-Point DSP Design Flow Validated by BDTI, Industry's Most Trusted Source of Independent DSP Technology Analysis
San Jose, Calif., September 12, 2011—Altera Corporation (NASDAQ: ALTR) today demonstrated its new floating-point digital signal processing (DSP) design flow using FPGAs, the industry's first model-based floating-point design tool that allows implementation of complex floating-point DSP algorithms on an FPGA. Independent analysis conducted by Berkeley Design Technology, Inc. (BDTI) validates the high performance, efficiency and ease of implementing floating-point DSP designs in Altera's Stratix® and Arria® FPGA families.The floating-point DSP design flow includes Altera's floating-point DSP compiler, which is integrated into the DSP Builder Advanced Blockset, Quartus ® II RTL tool chain, and ModelSim simulator, as well as MATLAB and Simulink tools from MathWorks to simplify the DSP algorithm-implementation process on FPGAs. The floating-point design flow combines and integrates the algorithm modeling and simulation, RTL generation, synthesis, place and route, and design verification stages. The integration enables quick development and rapid design-space exploration, both at the algorithmic level and at the FPGA level, and ultimately reduces overall design effort.
“Using Altera's high-level DSP model-based flow, designers can implement and verify complex floating-point algorithms more efficiently and quickly than would be possible with traditional HDL-based design,” said Vince Hu, vice president of product and corporate marketing at Altera. “Once the algorithm is modeled and debugged at a high level, the design can be easily synthesized and targeted to any Altera FPGA.”
Altera's new design flow is ideally suited to the demanding linear algebra problems typically requiring the dynamic range offered by floating-point DSP. BDTI benchmarked a parameterizable floating-point matrix-inversion design. Matrix inversion is representative of the type of processing used in radar systems, multiple-input, multiple output (MIMO) wireless systems, medical imaging and many other DSP applications.
In the evaluation of Altera's floating-point design flow, independent technology analysis firm BDTI stated, “Rather than building a datapath consisting of elementary floating-point operators…, the floating-point compiler generates a fused datapath that combines elementary operators into a single function or datapath. In doing so, it eliminates the redundancies present in traditional floating-point FPGA designs.” BDTI concluded, “With the fused datapath methodology, complex floating-point datapaths are implemented with higher performance and efficiency than previously possible.”
Read BDTI's complete FPGA floating-point DSP design flow analysis at www.altera.com/floatingpoint.
About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
|
Intel FPGA Hot IP
Related News
- Altera Demonstrates Industry's First QPI 1.1 FPGA Home Agent for Enhanced Server Capabilities
- Altera Introduces Industry's First FPGA Floating-Point FFT IP Cores
- Intilop's 10G Full TCP Accelerators with Network Security Features IP Core for Altera/Intel FPGAs qualified by major University and Government clients
- Altera Discloses Industry's First Heterogeneous SiP Devices that Integrate HBM2 DRAM with FPGAs
- Altera FPGAs Help Enable Deployment of Harris Corporation's Latest Falcon III Wideband Tactical Radio
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |