Open-Silicon Awarded Patent for Low Power ASIC Design Methodology
PowerMAX™ enables design for the lowest possible power
MILPITAS, Calif. – September 14, 2011 – Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has issued U.S. Patent 7,941,776 related to Open-Silicon’s PowerMAX technology. Low power SoC design is a key differentiator for not just mobile applications, but also many networking, telecom, storage, and computing solutions. This new Open-Silicon patent focuses on lowering SoC dynamic and standby power by enriching the target standard library to best fit the needs of a particular design.
Specifically, this patent encompasses the intellectual property rights of Open-Silicon’s ZenCells™, standard cells created on-the-fly using PowerMAX’s design-specific library augmentation. ZenCells drive down both dynamic and leakage power through a method of closed-loop IC design optimization via the creation of design-specific cells from post-layout patterns. This optimization process involves automatically creating design-specific cells with desired characteristics, such as power, performance, or noise, which are then implemented as a standard cell from a set of post layout patterns. The pattern represents a part of or a whole standard cell and contains information regarding the pattern, such as layout, timing area, power and noise. Because these cells are created from post-layout patterns, the risks of prior dynamic library techniques are easily avoided. The result is cells that are optimized to satisfy the constraints imposed by the design context, thus bringing powerful design-specific customization to standard cell-based design methodology.
Introduced in 2008, PowerMAX is part of Open-Silicon’s Max Technologies product line – a result of extensive R&D to create a series of products that allow customers to take their designs to a level beyond what the latest EDA tools offer. Based on a strong foundation of conventional techniques, PowerMAX adds design-specific library augmentation, back biasing, power recovery and custom leakage signoff, resulting in the ASIC industry’s most complete low power design offering. The total Open-Silicon PowerMAX offering includes both the conventional techniques and the new technologies. By combining the best industry standard methods with novel technologies unique to Open-Silicon, customers can achieve the lowest power consumption possible for their silicon.
“Increasing levels of integration in performance-driven SoCs have challenged designers to come up with novel architectural and physical design solutions for power density limitations. At the other end of the spectrum, mobile applications are driving exponential growth in mobile performance, matched with every-increasing battery life requirements,” said Colin Baldwin, director of marketing for Open-Silicon. “Open-Silicon identified this growing problem early on and developed the MAX technologies to solve it. The award of this patent underscores Open-Silicon’s commitment to low power technology, and the company’s ability to provide its customers with better custom silicon.”
About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.
|
Related News
- Dolphin Integration Receives Open-Silicon's Award for the Emerging IP Partner of the Year 2016 in the Low Power IoT Ecosystem
- Open-Silicon Enables Solarflare’s Low Power 10Gb Ethernet Solutions
- Innosilicon's Bitcoin ASIC powered by Samsung's Low Power FinFET technology to achieve record breaking performance
- Open-Silicon, Credo and IQ-Analog Showcase Complete End-to-End Networking ASIC Solutions at OFC 2018
- Open-Silicon to Showcase Breadth of ASIC Solutions at CDNLive 2016, Bangalore, India
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |