Cadence Announces DFI 3.0-compliant Design and Verification IP
Enables Rapid Deployment of Next-Generation SoCs Supporting DDR4 Memory
SAN JOSE, Calif. -- Sep 20 ,2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced it is offering a comprehensive suite of solutions in support of the latest DDR PHY Interface (DFI) 3.0 specification (also announced today by the DFI Technical Group). Enabling the development of chips and systems to support the emerging DDR4 memory standard, the specification defines an interface protocol between DDR memory controllers and PHYs. Cadence supports the specification across its DDR DRAM Controller IP, DDR PHY IP, and as part of the Cadence Verification IP Catalog. Cadence introduced the industry’s first DDR4 IP memory solution in April of this year.
“Our customers require DFI-compliant design and verification IP that will enable them to be first to market with next-generation SoCs that support the emerging DDR4 standard,” said Marc Greenberg, director of marketing, SoC Realization, Cadence. “Our close working relationship with the DFI Technical Group ensures that we offer integration-ready DFI solutions when the specification becomes available.”
DFI interface adoption continues to rise as designers seek ways to reduce the time-to-market and cost of their SoCs. Cadence has over 400 design wins for DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface. This makes DFI 3.0 support critical to customers who must deliver solutions in support of the emerging DDR4 standard.
About DFI 3.0
DFI 3.0 defines methods for interfacing to DDR4 devices with proposed data rates up to 3.2 Gbits/second per pin – more than 50 percent faster than the current DDR3 standard – and extends the low-power interface that was introduced with DFI 2.1. By accounting for frequency and power challenges at high speeds, the new standard helps ensure exceptional performance in systems using DDR4 memory. The preliminary specification is available now for download at www.ddr-phy.org.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Design Systems, Inc. Hot IP
Cadence Design Systems, Inc. Hot Verification IP
Related News
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification
- DB GlobalChip Deploys Cadence's Spectre FX and AMS Designer, Accelerating IP Verification by 2X
- Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud
- Cadence Verisium AI-Driven Verification Platform Accelerates Debug Productivity for Renesas
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |