Memoir Systems Introduces Groundbreaking Technology for Networking and Multicore SoC Products
Newly introduced embedded memory IP solutions offer unparalleled performance for network processors, switches and multicore processor products
SANTA CLARA, Calif., Oct 03, 2011 -- Memoir Systems(R) Inc., a Semiconductor Intellectual Property (SIP) venture-backed start-up with technology that delivers breakthrough embedded memory performance, today announced its initial targeted products. The company's patent-pending Algorithmic Memory(TM) technology provides an order of magnitude increase in embedded memory performance. Memoir's technology can also lower embedded memory area and power consumption, shorten memory development time, and provide versatility benefits. As a result, for its initial product applications, the company is focusing on networking SoCs (such as network processors, switches and Storage Area Network (SAN) switches), and multicore processor products.
Memoir CEO, Adam Kablanian explained, "We are literally writing a whole new chapter for the embedded memory market. The versatility and strength of our technology can deliver next-generation memory performance to system architects and memory design engineers who are developing SoCs. We believe that networking and multicore are the two product segments that can initially benefit most from our solutions."
Embedded memory performance has become the limiting factor in overall system performance for SoC designs. Memoir addresses this limitation with its patent-pending technology that utilizes the power of algorithms. Algorithmic Memory is implemented as standard RTL logic wrapped around existing embedded memory macros. It presents multiple memory interfaces that can all be accessed simultaneously, giving up to 10X more Memory Operations Per Second (MOPS).
Lightspeed Venture Partners, a leading global venture capital firm managing over $2-billion of capital commitments is a major investor in Memoir Systems. Barry Eggers, managing director for Lightspeed stated, "We invested in Memoir for two key reasons: The Memoir team brings world-class expertise in the area of memory algorithms, and its unique patent-pending technology can be leveraged across a broad set of current and future memory applications. We believe that this combination of team and technology puts Memoir in a position to disrupt some very large markets."
Sundar Iyer, co-founder and CTO for Memoir Systems noted, "With Memoir's Algorithmic Memory technology, memory performance is viewed as a configurable entity. System architects and SoC designers only need to specify their ideal memory performance characteristics, read/write interface configurations and any special requirements regarding area and power characteristics." Da Chuang, co-founder and COO stated that, "Memoir's synthesis platform can automatically select suitable memory macros from a memory IP library, and incorporate our memory algorithms to synthesize a new memory that is custom-made for the targeted application."
Overview on Initial Targeted Products
Embedded memory performance is a limiting factor in networking SoC applications. With ever increasing network line speeds, architects of network switches are finding it harder to process incoming packets fast enough to avoid overruns. For example, on a 4x100 Gb/s line card, new packets can arrive at the system every 1.6 nanoseconds. In addition, packet processing systems support a wide range of header applications - such as Lookups, Netflow, Statistics Counters, Traffic Management, etc. and payload processing applications such as Intrusion Detection, Content-based Load Balancing and Virus Scanning resulting in tens of memory accesses per packet. Faster processors alone cannot improve network performance unless the total Memory Operations Per Second (MOPS) are increased. Memoir's Algorithmic Memories offer system architects more MOPS, custom memory sizes, and multiple read, write interfaces.
High speed multicore processors are a game changer in the desktop, server, and embedded computing worlds. However, the overall performance of these SoCs can stall under heavy workloads due to contention over shared memory resources such as L2 or L3 caches. System architects can achieve even better performance, if these memory bottlenecks could be avoided. Memoir's Algorithmic Memory technology can solve this problem by increasing the MOPS of existing cache memories. This allows simultaneous memory accesses from all cores, increasing overall SoC performance.
About Memoir Systems, Inc.
Memoir Systems, Inc. is a provider of breakthrough embedded memory technology that is delivered as Semiconductor Intellectual Property (SIP). The company utilizes its patent-pending Algorithmic Memory(TM) technology to increase the performance of existing memory macros -- up to 10X more Memory Operations Per Second (MOPS). In addition, the technology significantly shortens memory development time, and lowers area and power consumption. Memoir's technology is process, node, and foundry independent, and can be readily integrated into any existing SoC (ASICs, ASSPs, GPPs and FPGAs) design flow. The company's strategy is to deliver technology and business benefits to its customers and partners by providing solutions that are drop-in replacements for existing embedded memory. Memoir Systems is based in Santa Clara, California, and has additional research and development facilities located in Hyderabad, India. For more information, visit www.memoir-systems.com .
|
Related News
- Open-Silicon to Demonstrate its High Bandwidth Memory (HBM2) IP Subsystem Solution for High Performance Computing and Networking Applications and Showcase its IoT Gateway SoC Reference Design for Smart City Applications at ARM TechCon 2017
- EZchip Introduces TILE-Mx100 World's Highest Core-Count ARM Processor Optimized for High-Performance Networking Applications
- Memoir Systems Introduces Renaissance Memory Uptime for Next Generation SoCs
- STMicroelectronics and Memoir Systems Combine Breakthrough Memory and Semiconductor Process Technologies
- Memoir Systems Introduces Renaissance for Datacom Memory IP Enabling Terabit Computing
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |