Asserting trio of standards

Standardizing assertions is important because, as I said in an earlier column, we now have a "Tower of Babel" situation, in which multiple vendors are pushing their own assertion formats and languages. That means assertions have to be rewritten for each tool, and you have to lea rn a new assertion language for each vendor. What's needed is a consistent way of writing assertions across the design flow.

Accellera's Verilog Formal Verification (VFV) committee is taking one step in that direction by trying to formulate a standard formal property language. After eliminating candidates from Intel and Verisity, they are now looking at IBM's Sugar and Motorola's CBV. Note that those are new languages, not extensions to Verilog or VHDL. The eventual standard will allow engineers to describe complex temporal properties, and it will most likely be used by systems engineers, not RTL designers.

A second effort unfolded earlier this month, as Co-Design Automation and Real Intent donated the Superlog Design Assertion Subset (DAS) to Accellera's System Verilog committee. That is an attempt to add an assertion mechanism to Verilog, which currently does not have one. It doesn't require Superlog and will work with any Verilog tool, but not with VHDL.

Then there's the Open Verif ication Library (OVL), a library of open-source assertion primitives created by Verplex Systems. It was originally created for Verilog and now supports VHDL. Anyone can use it now by going to the Web site: www.verificationlib.com.

At this juncture, several things need to happen. First, while a coalition of small vendors is supporting the DAS, there needs to be buy-in from Synopsys, Cadence and Mentor Graphics on all of those standards efforts. Second, users need to declare loud and clear that their vendors are going to have to conform to standards. Third, the formal property language, the DAS, and the OVL all must work together.