English
Faraday Technology Adopts ATopTech's Aprisa for Physical Implementation at Advanced Process Nodes
Aprisa shortens turn-around time and improves quality of results, leading to successful tapeout in UMC’s 40nm process
SAN JOSE, CA – October 17, 2011 — ATopTech, the leader in next-generation physical design solutions that address the challenges of designing integrated circuits (ICs), announced today that Faraday Technology Corp. has adopted ATopTech’s Aprisa physical design solution as the company’s tool of choice for physical implementation at advanced process nodes. Faraday Technology Corp. is one of the largest leading silicon IP and fabless ASIC provider in the Asia-Pacific region.
40nm technology helps design engineers satisfy their customers’ continuous demands of higher performance, lower power consumption and lower manufacturing cost. However, designs at 40nm impose tremendous challenges, such as increased cross-talk effect and process variation, which, if not addressed properly, may cause compromised quality of results and delay in design closure. It is exactly these areas that Aprisa, ATopTech’s advanced netlist-to-GDSII physical implementation tool, consistently demonstrates: superior routing ability and excellent timing closure. Faraday’s extensive evaluation of Aprisa was further validated when Aprisa delivered better design quality and more predictable design closure with a successful design tapeout in UMC’s 40nm process.
“Complicated physical effects and demanding design specifications present increased challenges for 40nm design projects,” said Kun-Cheng Wu, associate vice president of Faraday Technology Corp. “We are pleased with the improved quality of results and turn-around time we’ve gained by adopting Aprisa as our physical implementation tool.”
“ATopTech’s place and route technology was architected specifically for advanced technologies,” said Jue-Hsien Chern, CEO of ATopTech, Inc. “We are fully committed to helping Faraday to achieve further successes in 40nm and other design projects.”
About Aprisa
Aprisa is a complete place-and-route (P&R engine), including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines”, such as RC extraction, design rule checking (DRC) engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
About ATopTech
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
About Faraday Technology
Faraday Technology Corporation is one of the largest leading silicon IP and fabless ASIC provider in the Asia-Pacific region. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S. , Japan , Europe, and China . For more information, please visit: www.faraday-tech.com
Related News
- Advanced DDR Memory Interface PHY's and Controllers IP Cores available in advanced process nodes including TSMC 7FFC
- Arasan Announces Advanced Process Nodes for High Performance SD Card UHS-II Physical Layer Interface
- Achronix and Mentor Graphics provide state of the art physical synthesis support for Speedster22i FPGAs - the world's most advanced FPGAs leveraging Intel's 22nm process technology
- Virage Logic Supports TSMC's Power Trim Service(TM) for Advanced Process Nodes
- Faraday Adds Video Interface IP to Support All Advanced Planar Nodes on UMC Platform
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |