ANSYS Subsidiary Apache Design Launches RTL Power Model, Enabling Early Planning and Accelerating Ultra-Low Power Design Delivery

New Technology Facilitates Predictable Power Budgeting, Reduced Cost and Faster Time to Market for Leading IC Applications

Pittsburgh – November 8, 2011 – ANSYS (NASDAQ: ANSS) subsidiary Apache Design Inc. launched RTL Power Model (RPM™), a first-in-class innovative technology designed to optimize a wide range of power-sensitive applications, such as ultra-low-power electronics. RPM bridges the power gap from register-transfer-language (RTL) design to physical implementation. The new technology accurately predicts integrated circuit (IC) power behavior at the RTL level with consideration for how the design is physically implemented. As a result, the technology helps to enable chip power delivery network (PDN) and IC package design decisions early in the design process, as well as to ensure chip power integrity sign-off for sub-28nm ICs.

Due to extensive ultra-low-power requirements and shortened design cycles, it is critical to make power design trade-offs, such as dynamic voltage/frequency scaling, clock-gating/power-gating schemes, and package selection, early in the design cycle, when changes are easier to make and have less impact on schedule or cost.

“Apache’s innovative approach provides a complete front- to back-end power analysis flow,” said Ruggero Castagnetti, distinguished engineer, LSI Corporation. “The ability to understand the impact of low-power architecture selection and chip operating modes on power grid and package design trade-offs early in the flow allows LSI to better predict system cost and improve productivity.” 

Innovative Technology

As a new offering to Apache’s PowerArtist™-XP software, RPM’s core technologies include PowerArtist Calibrator and Estimator (PACE™) for accurate power estimation at the RTL level prior to availability of physical layout as well as Fast Frame-Selector for critical power-aware cycle selection.

PACE uses proprietary data-mining and pre-characterization techniques to create higher-quality power and capacitance models, as compared to traditional wire load models tuned for timing closure. By considering characteristics for various circuit types, such as combinational logic and sequential elements, PACE delivers RTL power within 15 percent of gate-level power, leading to more cost-effective and higher-quality results.

Fast Frame-Selector technology performs power analysis on RTL simulation vectors and selects a set of the most power-critical cycles to use throughout the design flow, from early design planning to final chip sign-off. It can accurately identify a few cycles representing the transient and peak power characteristics from millions of vectors within hours, improving productivity and ensuring power sign-off integrity.

Advanced Methodology

RPM enables a comprehensive power methodology from early design to sign-off by providing physical-aware RTL power data. Apache’s RedHawk™ leverages RPM to perform PDN prototyping then generates an early-stage Chip Power Model (CPM™) that is used by Sentinel™ software for IC package design planning, such as substrate layer selection and decap optimization. RedHawk also utilizes RPM to provide more-realistic switching activities for accurate power sign-off.

“The introduction of RPM demonstrates Apache’s continued commitment to delivering innovative key technologies that address the critical low-power design challenges,” said Vic Kulkarni, senior vice president of RTL business at Apache Design. “Apache’s power budgeting flow allows customers to right-size their power delivery network, improving design performance and mitigating chip failure risks.”

Low-Power Application Optimization

Designing for low-power applications requires a methodology that addresses power budgeting and allows timely cost-sensitive decisions related to power. PowerArtist-XP software with RPM technology is ideal for advanced node designs of low-power applications including mobile, green computing, and consumer electronics devices. It helps bridge the gap from front-end RTL design to physical power sign-off, with more predictable accuracy, increased operating performance, and greater reliability for 28nm and below designs.