Open-Silicon's Interlaken IP Core Chosen for ALAXALA's Advanced Networking Infrastructure Device
Open-Silicon’s High Speed Interconnect Protocol Ideal for “The Guaranteed Network”
MILPITAS, Calif. – December 6, 2011: Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today ALAXALA Networks has integrated its Interlaken Controller IP into their next generation of high-performance network products. Taking advantage of the high-speed and scalability of the Interlaken interface, as well as Open-Silicon’s strong support team, ALAXALA was able to rapidly develop an ASIC that enables next-generation performance levels for their systems.
The Interlaken protocol is an integral part of today’s leading edge data networking products, enabling fast, scalable, and low-latency chip-to-chip communication for switching, routing, and deep packet processing applications. Architected to be easily synthesizable into many ASIC technologies, Open-Silicon’s Interlaken IP core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. This support for multiple industry-leading SerDes PHYs allows Open-Silicon’s customers to quickly integrate the core into their technology of choice.
“Since being introduced in 2006, Interlaken has grown significantly in its adoption and has proven to be a reliable solution for both high-bandwidth data streaming and look-aside interface applications. Networking devices which require zero down time and scalable performance can all benefit from the robust and flexible capabilities of the Open-Silicon Interlaken IP core,” said Jason Pecor, business development manager, Open-Silicon.
“ALAXALA is known for providing exceptionally reliable, high-performance routers and switches that operate at the heart of corporate networks and the networks of service providers and telecom carriers. Our use of this Interlaken Controller IP, along with Open-Silicon’s strong support team, helps ALAXALA drive network evolution and underscores our mission of providing ‘The Guaranteed Network,’” said Takashi Kumagai, department manager of LSI Design, ALAXALA Networks.
About the ASIC Interlaken IP Core
Combining the advantages of popular SPI4.2 and XAUI interfaces, the Interlaken protocol builds on the channelization and per channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology. Open-Silicon’s Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.
The Open-Silicon Interlaken Protocol Controller IP supports the following Interlaken Alliance specifications:
- Interlaken Protocol Definition, v1.2
- Interlaken Look-Aside Protocol Definition, v1.1
- Interlaken Interop Recommendations, v1.4
Additional details regarding Open-Silicon’s Interlaken IP core can be found at http://www.open-silicon.com/capabilities/ip/interlaken-controller-ip.html.
About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.
|
Related News
- Open-Silicon's Configurable Interlaken IP Core Delivers High-Performance Chip to Chip Interface for Networking Products at 28nm Process Node
- Open-Silicon Expands Networking IP Portfolio to Address High-Bandwidth Ethernet Endpoint and Ethernet Transport Applications
- Open-Silicon Unveils Industry's Highest Performance Interlaken Chip-to-Chip Interface IP
- Open-Silicon's Interlaken IP Core Selected for Netronome's Next-Generation Flow Processors
- Open-Silicon Unveils Interlaken IP Core with 600 Gbps Chip-to-Chip Interface Support for Networking, Storage and High-Performance Computing Products
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |