InnoRoute announces the availability of its FlowEngine packet flow processor family
Munich – Germany – December 12, 2011 – InnoRoute, a startup specialized in Ethernet QoS packet processing technology for service provider and telecom networks today announced the availability of the IR-FExG Flow Engine product family.
Addressing the access part of the telecom network in MDUs and DSLAMs as well as base-station backhauling, this highly innovative solution enables system manufacturers to reduce cost and complexity compared to common network processor approaches.
The InnoRoute FlowEngine IR-FExG is an Ethernet packet processor core element that is used to extend the functionality of a standard layer-2 Ethernet switch to provide G.999.1 connectivity over Gigabit-Ethernet interfaces, ATM AAL5 segmentation and reassembly for legacy ADSL operation and a highly innovative QoS functionality based on InnoRoute FlowShaper architecture.
To reduce cost and complexity, more and more system manufacturers of access edge components like MDUs, DSLAM or mobile transmission nodes want to use standard layer-2 Ethernet switch components in their access systems. Also there is a benefit to match the handling of the aggregation part to the uplink architecture, which is mainly set up by Carrier Ethernet components. But on one hand even highly sophisticated Ethernet switch devices lack of flexible back-pressure functionality which is needed to connect for example xDSL PHYs. On the other hand they do not provide QoS that can be applied to a large number of very different service scenarios for many different connections.
InnoRoute has created the FlowEngine family to cover both aspects in a highly efficient way, matching the interface needs as well as providing simple but robust QoS functionality by InnoRoute FlowShaper technology.
The FlowShaper element inside the FlowEngine packet processor creates a new paradigm for carriers and operators in terms of handling the configuration of high performance QoS functionality. Instead of intense effort to prepare the parameters for commonly available QoS solutions, with InnoRoute FlowShaper concept a self-configuring scheduler provides queues with guaranteed latency times. This reduces the effort for carriers and network operators dramatically and will open the path for high-end traffic shaping in the access network parts.
Availability
The IR-FE10G is currently available for Xilinx Spartan-6 family and provides either 1x XAUI or 8x SGMII interfaces to extend the functionality of a standard layer-2 switch.
The IR-FE2.5G version can be used without a layer-2 switch to completely cover the aggregation part in a small port count MDU or mini-DSLAM. It provides 4x xGMII interfaces and thus can connect 2 or 3 xDSL PHY devices.
About InnoRoute
InnoRoute is a provider of highly innovative packet processing technology enabling the next and future generations of telecom carrier and service provider networks. The InnoRoute flow engine architecture provides a combination of multi-Gigabit throughput and best-in-class Quality-of-Service (QoS) functionality. InnoRoute was founded in 2010 and is headquartered in Munich, Germany.
|
Related News
- Imagination announces latest licensing deal with NXP
- Cortus Announces the General Availability of a RISC-V Processor Family - from Low End Embedded Controller to 64 bit Processor with Floating Point.
- Posedge Inc announces the availability of "Wireless Packet Processor"
- MIPS Technologies' Announces Availability of 850MHz MIPS32(R) 24KE(TM) Processor Core Family
- Actel Delivers Secure, Comprehensive Design Flow for Complex FPGA Development Using ARM7 Family Processor
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |