The Process of FPGA Design Takes Giant Leap Forward With the New Stellar IP Tool from 4DSP
December 12, 2011 -- Austin, TX, USA – 4DSP LLC takes another giant leap forward in simplifying the process of FPGA design by releasing their new Stellar IP tool. Stellar IP is designed to automate the creation of an FPGA image by reusing proven IP cores. It offers a platform for software engineers to target FPGA devices.
In recent years, the substantial growth of resources available inside FPGA devices has forced engineers to change the way they approach programmable logic design. A higher level of abstraction and the removal of error prone tasks are critical to the success and timely completion of projects. FPGA technology has often been decried in the past for its implementation slowness from concept to release. Relying on existing IP to speed up this process has become essential and ensures that the FPGA portion of the system does not become the schedule bottleneck. Stellar IP does not claim it will solve all inherent problems of FPGA design but it guarantees that its simplicity of use will help engineers complete their project faster by removing tedious steps out of the cycle.
Knowledge of a HDL language is not required for using Stellar IP. This provides software engineers with the ability to create new FPGA designs by relying on existing IP and extend their domain of influence to the entire system.
"Programming a software for a Stellar IP based design is as simple as using a microcontroller. Designing a StellarIP FPGA firmware is even easier since it’s only about interconnecting IP blocks to one another, either by using a text file or a graphical schematics editor. The tool takes care of the rest and prevents the user from having to deal with the intricacies of FPGA design" said Arnaud Maye, Embedded Systems Manager at 4DSP.
Stellar IP offers many benefits such as simplifying the integration of new cores that can be reused across multiple designs. It provides a library of off-the-shelf IP cores and automates the creation and compilation of ISE projects in addition to simulation scripts.
Stellar IP is available for free as part of the 4DSP Board Support Package targeting the 4DSP FMC and Virtex-6 FPGA product lines (http://www.4dsp.com/fmc, http://www.4dsp.com/v6). It can be licensed for use with third party products.
This is a great opportunity for FPGA engineers to solidify their FPGA firmware. A short video and technical information about Stellar IP can be found at http://www.4dsp.com/stellarip.php.
About 4DSP LLC
4DSP is an innovative company specializing in low power, low weight and compact FPGA based signal and image processing systems. Headquartered in Austin, Texas, USA, with offices in the Netherlands, 4DSP is a developer of reconfigurable computers of advanced architecture which offer customers maximum flexibility and scalability. 4DSP's hardware platforms deliver unmatched performance for advanced digital signal processing (DSP) applications in embedded computing applications. More information about 4DSP can be found at http://www.4dsp.com.
Related News
- RISC-V Takes a Leap Forward
- Thread Group Takes Leap Forward with Availability of First Certified Software Stacks from ARM, NXP, OpenThread and Silicon Labs; Launches Product Certification Program
- eMemory's Security-Enhanced OTP Qualifies on TSMC N4P Process, Pushing Forward in High-Performance Leading Technology
- RISC-V Pioneer SiFive Takes Stock, Realigns, Moves Forward
- Microchip Adds Second Development Tool Offering for Designers Using Its Low-Power PolarFire RISC-V SoC FPGA for Embedded Vision Applications at the Edge
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |