ECC Tek Announces Ultra-High-Performance Binary BCH Encoders and Decoders
December 19, 2011 -- ECC Technologies, Inc. (ECC Tek) announces the immediate availability of ultra-high-performance binary BCH encoders and decoders for correcting large numbers of random errors in MLC NAND Flash memories. ECC Tek has developed numerous programmable binary BCH designs which are programmable to correct up to 72 bits in error in short (512+ Byte) and long (1024+ Byte) pages.
ECC Tek has nearly 8 years experience designing binary BCH encoders and decoders and has incorporated many gate-saving and performance-enhancing improvements in its latest designs. All of ECC Tek's binary BCH decoders can correct the maximum number of errors in continuous incoming pages with no slowdown of the input.
Binary BCH designs that correct a large number of random errors probably require approximately 1/3 the number of gates and 1/3 the amount of power of an equivalent performance LDPC decoder. In addition, with binary BCH codes, you can be 100% certain that all error patterns with t or fewer errors will be corrected. I do not believe LDPC decoders can make that claim. Also, binary BCH decoders will signal failure if more than t errors occur with a very high probability of success (almost 100%). Again, I do not believe LDPC decoders can do that.
ECC Tek can easily customize its binary BCH designs for each licensee. The level of parallelism can be adjusted in each component. Higher levels of parallelism increase performance and gate count. Inputs can be any number of bits wide. Current implementations input and output bytes.
All of ECC Tek's decoders feature a variable latency so that the time to decode only depends on the number of errors that actually occur. Most other decoder designs do not and probably cannot provide this feature. Fixed latency can also easily be implemented.
ECC Tek's binary BCH designs are solid, sound, proven, field-tested and millions are currently in mass production. If you use a digital camera, thumb drive or MP3 player, there's a chance you are already using ECC Tek's designs. In over 20 years of licensing ECC designs, no licensee has had any problems with ECC Tek's designs, and all licensees have been happy with the results. In most cases, ECC Tek's designs have significantly outperformed the licensee's requirements and expectations.
Binary BCH encoders and decoders that correct from 8 to 72 bits in error in short and long pages are immediately available. Existing designs can easily be modified to correct more than 72 bits in error.
Related News
- intoPIX Releases a New Range of Compact Encoders and Decoders for JPEG XS
- Cyclic Design Announces Enhanced BCH ECC Portfolio: G14X IP Supports 64-bit Error Correction for NAND Flash Applications
- Cyclic Design Releases Advanced BCH Error Correction IP for Next Generation NAND Flash Applications
- DVB-S2X LDPC/ BCH Encoder and Decoder IP Core Available For Integration From Global IP Core
- CAST NAND Flash Controller Supports Latest High-Speed Memories and is Ready for ONFI 3
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |