TransEDA Introduces VN-Cover Simulation Farm Bundle for Faster Design Verification at 80 Percent Savings

Engineers Can Now Measure Coverage on 50 Machines for One Low Price

LOS GATOS, Calif. - April 2, 2002 - TransEDA®, the leader in ready-to-use verification solutions for electronic designs, today announced its VN-Cover Simulation Farm Bundle, offering engineers performing functional verification on simulation farms an 80 percent cost savings for coverage on up to 50 simulation servers. The VN-Cover Simulation Farm Bundle includes one full license of TransEDA's VN-Cover™ coverage analysis solution and 49 additional simulation drivers.

 Driven by an explosion in difficulty, the verification of complex SoCs is increasingly taking place on simulation farms of tens to hundreds of servers. With stimulus partitioned across servers, the verification process can be sped dramatically, but the cost of providing a separate license for coverage analysis on each machine can be prohibitive. "The availability of inexpensive Linux-based PCs and the EDA tools that run on them are making simulation farms available to a wider audience," said Tom Borgstrom, vice president of marketing at TransEDA. "Engineers using simulation farms need to be able to run coverage on all of their machines to be able to measure verification progress. With the VN-Cover Simulation Farm Bundle we are providing these engineers a way to combine the verification throughput of a simulation farm with the benefits of complete coverage analysis at a very reasonable price."

 The VN-Cover Simulation Farm Bundle is ready-to-use with existing simulation environments and verification flows. The solution supports a heterogeneous network of hardware platforms, with support for Linux, Solaris, HP-UX, AIX and Windows NT, and all of the industry-leading HDL simulators. VN-Cover is the industry's leading Verilog, VHDL and dual-language coverage analysis solution and offers a wide array of advanced coverage metrics including statement, branch, toggle, condition, path, signal trace, triggering, FSM and FSM path coverage.

VN-Cover includes a graphical user interface, a simulation driver, and analysis capabilities that enable designers to identify and focus test development effort on the areas of a design that have yet to be fully simulated, slashing the number of simulation iterations required. Combining its capabilities with 49 additional simulation drivers means an engineer can concurrently run simulations of a design across a network of up to 50 servers, collecting coverage data without the need to purchase 50 full VN-Cover licenses.

 About Verification Navigator™
TransEDA's Verification Navigator integrated design verification environment features tools that enable IC designers to manage the verification process and shorten verification time. In addition to VN-Cover, Verification Navigator includes VN-Check™ configurable HDL checking, VN-Optimize™ test suite analysis, VN-Property DX™ dynamic property checking, and VN-Control™ application-specific test automation. Verification Navigator supports all leading Verilog, VHDL, and dual-language simulators and is available on the Solaris, HP-UX, AIX, Linux, Windows NT, and Windows 2000 platforms.

 Pricing and Availability
The VN-Cover Simulation Farm Bundle, featuring one full license of VN-Cover plus 49 simulation drivers, is available now through June 30, 2002, in Verilog, VHDL, language neutral, and dual language configurations. Pricing starts at $100,000 for a single-language perpetual license, an 80 percent savings off list price. Subscription-based pricing is also available.

 About TransEDA
TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets ready-to-use design verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models and properties for advanced microprocessors and standard bus interfaces.

 TransEDA's design verification software performs application-specific test automation, configurable HDL checking, dynamic property checking, code and finite state machine (FSM) coverage analysis, and test suite analysis. TransEDA's tier-one customers include 18 of the world's top 20 semiconductor vendors.

For more information, visit www.transeda.com or contact TransEDA at 985 University Avenue, Los Gatos, Calif. 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, e-mail info@transeda.com.

 Note: TransEDA and Verification Navigator are registered trademarks and Foundation Models, VN-Property DX, VN-Check, VN-Cover, and VN-Optimize are trademarks of TransEDA. All other trademarks are properties of their respective holders.
 

MEDIA CONTACTS:

In North America, Asia, and Japan:
TransEDA
Tom Borgstrom
408.335.1303
tom.borgstrom@transeda.com

 Armstrong Kendall, Inc.
Jen Bernier
408.975.9863
jen@akipr.com

 In the U.K. and Europe:
PentaCom
Sharon Graves
+44 1242 525205
sharon.graves@pentacomagency.com