IP Cores, Inc. Ships More True Random IP Cores
IP Cores, Inc. announces growth in design wins for its true random IP cores.
Palo Alto, California -- December 27, 2011 -- IP Cores, Inc., California, USA (http://www.ipcores.com) has reported steady growth in design wins for its flagship true random number generator IP core, TRNG1.
“Our true random generator IP cores are in high demand among ASIC and FPGA designers looking for a true random number source to use in cryptographic applications,” said Dmitri Varsanofiev, CTO of IP Cores, Inc. “Our innovative design of the hardware true random number generator (TRNG) requires no special handling during the physical design stages”.
True Random Number Generators
True Random Number Generators (TRNG) are critical security blocks typically utilized to generate random numbers for secret cryptographic keys as well as seeds for pseudo-random number generators. A good-quality random number generator is essential for security, since generating the keys from a poor random source will significantly reduce the entropy of the long keys and might allow a brute-force attack on the seed that generated the key. A typical embedded application usually does not have access to high-quality randomness sources, so a designer of a System-on-a-Chip (SoC) targeting such application might want to instantiate a true-random source on the chip.
Many TRNG designs rely exclusively on physical features. IP cores, Inc. in its TRNG1 design has avoided the potential sources of these problems thus allowing the back-end processing with little or no extra effort spent on TRNG1. For example, a typical FPGA instantiation of the TRNG1 requires no special scripts or tool configuration whatsoever.
Additional information about TRNG1 can be found on the IP Cores, Inc. web site, http://ipcores.com/True_Random_Generator_TRNG_IP_core.htm
About IP Cores, Inc.
IP Cores is a rapidly growing California company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 cryptographic hashes, lossless data compression cores, low-latency fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi decoder cores.
|
IP Cores, Inc. Hot IP
Related News
- CEA-Leti Launches OpenTRNG, an Open-Source Project For True Random Number Generators Using Ring-Oscillator-Based Architectures
- Xiphera contributes to Linux kernel
- Synopsys Accelerates FIPS 140-3 Certification with NIST-Validated True Random Number Generator IP
- Inside Secure releases latest True Random Number Generator providing continuous protection against security threats in IoT and Datacenters
- Athena Announces Advanced True Random Number Generator
Breaking News
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
- Qualcomm initiates global anti-trust complaint about Arm
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- SiliconIntervention Announces Availability of Silicon Based Fractal-D Audio Amplifier Evaluation Board
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Siemens acquires Altair to create most complete AI-powered portfolio of industrial software
- Alphawave Semi Reveals Suite of Optoelectronics Silicon Products addressing Hyperscaler Datacenter and AI Interconnect Market
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Rapidus Announces Strategic Partnership with Quest Global to Enable Advanced 2nm Solutions for the AI Chip Era
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |