English
MoSys Demonstrates Interoperability of its Bandwidth Engine(R) IC at DesignCon 2012
SANTA CLARA, Calif., Jan 30, 2012 -- MoSys , a provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, is exhibiting at DesignCon 2012 in booth 615. MoSys will demonstrate interoperability between its Bandwidth Engine® IC and the newest 28nm FPGAs from both Altera Corporation and Xilinx, Inc.
DesignCon is renowned as being the premier event for the semiconductor and electronic design engineering community. DesignCon 2012 is no exception. It is the largest meeting of board designers and is the only event to address chip design engineers' chip/system/package challenges. It is the place for this community to network, identify solutions to immediate design challenges, and meet in person the solution providers for your next project. DesignCon brings together engineers, suppliers, analysts and media from across the globe, including Asia and the Pacific Rim. DesignCon's exhibit floor offers the semiconductor and electronic design engineering communities a place to showcase their latest technological advancements and product developments.
DesignCon 2012 begins January 30, 2012 and concludes February 2, 2012. The exhibition takes place on January 31 and February 1, 2012.
Santa Clara Convention Center 5001 Great America Parkway Santa Clara, CA 95054
About MoSys, Inc.
MoSys, Inc. is a provider of high-performance networking memory solutions and high-speed, multi-protocol serial interface intellectual property (SerDes IP). MoSys' leading edge Bandwidth Engine(R) ICs combine the company's patented 1T-SRAM(R) high-density memory with its SerDes IP and are initially targeted at providing breakthroughs in bandwidth and access performance in next generation networking systems. MoSys' SerDes IP and DDR3 PHYs support a wide range of data rates across a variety of standards, while its 1T-SRAM memory cores provide a combination of high-density, low-power consumption, high-speed and low cost advantages for high-performance applications. MoSys is headquartered in Santa Clara, California. More information is available on MoSys' website at www.mosys.com.
|
||||||
Related News
- MoSys Demonstrates Bandwidth Engine IC Interoperability with LSI SerDes
- MoSys Demonstrates Bandwidth Engine IC Interoperability with Avago Technologies SerDes
- MoSys Demonstrates 15.625G Bandwidth Engine SerDes Interoperability with Xilinx's Kintex UltraScale FPGA at OFC 2014
- MoSys Unveils New Bandwidth Engine IC with On-Board Macro Functions for 400G Network Equipment
- MoSys Announces Second Generation Bandwidth Engine IC Delivering up to 384 Gbps Throughput in a Single Device
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |