NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Evatronix Announces the USB 3.0 Compatible High Speed Hub IP Core with Analog and Digital PHY Options
Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)
A standalone, USB 3.0-compatible High Speed hub offers two technology-agnostic implementation options and a tape-out ready combo IP with proprietary USB PHY for various technologies.
Bielsko-Biala/Poland, January 30th, 2011 - Evatronix SA, the renowned provider of over 250 licenses for USB IP solutions, have announced a synthesizable USB High Speed Hub that supports High Speed mode requirements of the USB 3.0 Hub specification, and features an aggressive power management function provided by Link Power Management (LPM) mode for all supported speed rates.
The new generation of the USB High Speed Hub offers single or multiple Transaction Translators and a configurable number of downstream ports (up to 15). For further customization of the hub, all its descriptors can be configured to the designer’s liking.
Thanks to its customizable architecture the hub can be provided in three versions: as a bare version with repeater-enhanced UTMI+ outputs, as a digital PHY enabled IP with pre-configured upstream and downstream UTMI PHY digital logic or as a complete, standalone hub targeted for particular technology together with the Evatronix USBHS-PHY.
The Low Power Management (LPM) feature secures the hub's compatibility with the USB 3.0 specification and thus enables designers to include the hub in the USB 3.0 hub IP as a part responsible for High, Full, and Low Speed transfers.
For immediate prototyping, a proprietary board can be delivered with test chip PHYs. With its CPU-less architecture, the design is ready for verification and testing in developer’s environment right out of the box.
“This completely redesigned USB 2.0 Hub combines all the best aspects of USB engineering developed at Evatronix in both digital and analog areas,” said Dariusz Kaczmarczyk, USB Product Line Manager at Evatronix. “Thanks to three available interface configurations, we are able to fit our Hub into any design, letting the customer decide which PHY he will use – ours or his.”
The previous generation USB 2.0 Hub from Evatronix will be available from now on only for embedded applications as the USBHS-HUB-E, and feature some advanced optimization towards such implementations.
ABOUT EVATRONIX USB SOLUTIONS
The Evatronix USB IP product suite consists of many varied, but complementary elements essential for a successful USB design. From USB-IF certified IP cores supporting all available speed rates, through integrated software stacks, to proprietary PHYs, Evatronix provides complete solutions for every USB-enabled SoC.
|
Related News
- Cadence Encounter Digital Implementation System Used by Gennum’s Snowbush IP Group to Speed Delivery of Industry’s First 45nm USB 3.0 PHY IP
- Evatronix Enhances its USB Portfolio with High Speed Inter-Chip (HSIC) Compatible PHY IP
- Faraday Technology and Fresco Logic Partner to Validate SuperSpeed USB PHY (USB 3.0) with SuperSpeed Digital xHCI Host and Device Controller
- Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores with Superfast speed and High-power efficiency for lag-less data processing is Silicon Proven and available in 8nm LPP for licensing
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |