New Integration Between SpaceStudio Hardware Software Co-design and European Space Agency’s TASTE Tool Set
Space Codesign® will introduce extensions to the TASTE methodology using SpaceStudio technology at the ERTS² 2012 Conference
Montreal, Quebec -- February 1, 2012 -- Space Codesign® Systems is pleased to announce the new integration of its SpaceStudio 2.2 ESL virtual platform technology with the European Space Agency(ESA)’s ASSERT Set of Tools for Engineering (TASTE). While the ESA is seeking to improve productivity by increasing automation of aerospace and satellite electronics development, the new extension and integration of SpaceStudio with TASTE enables engineers to model complex System on Chip (SoC) implementations. This integration works by allowing direct access to the design components of each node/board in the embedded system, thus dramatically reducing the development cycles.
SpaceStudio is a pioneering hardware/software co-design technology that enables electronic engineers to enjoy a higher level of abstraction and executable representation for embedded systems design in aerospace and commercial multimedia applications. ”Architects and system developers will mostly see the benefits of this integration in high-level models of VHDL IP-cores, high-level modeling of LEON processor and Virtual Platform technology that will be used for the runtime management of the IP models and simulation,” says Guy Bois, Ph.D., P. Eng., and President of Space Codesign® Systems. The integration with TASTE was achieved in partnership with M3 Systems (Toulouse, France) and the ESA (Paris, France).
Space Codesign® Systems will demonstrate this new integration with TASTE at the Embedded Real Time Software and Systems (ERTS²) conference in Toulouse (France). Together with the aforementioned partners, Space Codesign® Systems will present a paper summarizing a feasibility study that was performed on behalf of ESA, evaluating extensions to the TASTE methodology using SpaceStudio technology. The paper’s name is “The ASSERT Set of Tools for Engineering (TASTE): Demonstrator, HW/SW Codesign and Future Evolution” and it will be presented in Session 4A.3 on Thursday, February 2, between 10:30 – 12:30.
TASTE is recognized for its strengths in specifying complex distributed systems, and the integration with SpaceStudio enables SoC embedded systems fetch up the components of these distributed systems. ”Integrating SpaceStudio with the TASTE tool set will produce a complete solution by adding support for hardware subsystems and for co-designed hardware/software subsystems, leading to improved engineering productivity,” said Laurent Hili, VLSI/ASIC Engineer at the ESA’s Data Systems Division/ Micro Electronics Section.
Space Codesign® Systems will also be participating in the exhibition hall of the ERTS² conference (Booth 57). For more information, please visit the Space Codesign® Systems booth or visit the website at http://www.spacecodesign.com.
About Space Codesign:
Founded in 2008, Space Codesign® Systems, Inc. offers Virtual Platform technology products and services for the creation of embedded systems applications centered on ESL (Electronic System Level) design technology and hardware/software codesign methodology. Space Codesign® Systems’ technology was initially developed in the Microelectronics and Microsystems Group (GRM2) at École Polytechnique de Montréal, where SpaceStudio™ technology has matured to become a powerful and unique front-end design tool. The pioneering hw/sw codesign technology produced by Space Codesign® Systems enables electronic engineers to enjoy a higher level of abstraction and executable representation for embedded systems design in aerospace and commercial multimedia applications.
|
Related News
- Space Codesign Systems to Release Version 2.4
- SpaceStudio Hardware Software Codesign Tool Expands Offering to New SoC Design Markets
- Space Codesign Introduces the First Virtual Platform Technology Supporting Hardware/Software Codesign for FPGA Based on ARM Cortex-A9
- The European Space Agency (ESA) has awarded a contract to CAES, in the frame of the ARTES Competitiveness & Growth programme, to develop System-on-Chip for space applications
- European Space Agency, Blue Pearl Software and ADIUVO Engineering Partner Contract to Improve the usability of ESA Soft-Cores
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |