Mentor Graphics introduced v5.2 of its FPGA Advantage HDL design flow
FPGA Advantage
By David Larner, Embedded Systems
November 1, 2001 (9:00 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011101S0018
Mentor Graphics introduced v5.2 of its FPGA Advantage HDL design flow for creation, management, simulation and synthesis of FPGA designs. The new version has features that improve design creation and design reuse, and synthesis enhancements that generate more accurate timing data. To speed importation of legacy code into a new design, there is a recursive file search feature that can set up and search through a directory of IP. Mentor's TimeCloser synthesis technology has been extended to deal with Altera's Quartus-II design environment. V5.2 is available now. Mentor and Altera have joined each others partnership programmes. Altera became the seventh member of Mentor's Embedded Technology Adoption Program (ETAP). Altera will now give its embedded design customers access to an enhanced version of the Mentor's XRAY Debugger. Mentor's Embedded Software Division is also a founding member of Altera's newly created Excalibur Partner Program.
Related News
- Mentor Graphics, GateRocket Collaborate on Integrated Solution to Streamline FPGA Verification-Through-Synthesis Flow
- EnSilica's eSi-RISC embedded processors validated for Mentor Graphics' Precision Synthesis FPGA design flow
- Achronix and Mentor Partner to Provide Link Between High-Level Synthesis and FPGA Technology
- Mentor Graphics Expands Embedded Software Development Capabilities for Secure Industrial Applications
- Mentor Graphics Veloce Power Application Redefines Power Analysis Flow
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |