5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+
Calypto Delivers Bus Interface Libraries to Easily Connect High Level Synthesis Models to ARM Platform
SANTA CLARA, Calif., – February 27, 2012 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, today announced bus interface libraries that connect hardware subsystems implemented with Calypto’s High Level Synthesis product (HLS), Catapult® Synthesis, with AMBA® AXI™ bus interfaces. The libraries include master and slave interfaces with both Transaction Level Modeling (TLM) and HLS views, which allows easy interplay between a TLM 2.0 platform and HLS implementation flow without degrading simulation performance or hardware quality. The highly parameterizable AXI interface supports a wide range of configurations including burst modes, bus width and auxiliary control signals.
“The AXI interfaces are the first in a series of libraries in development at Calypto that will make Catapult C more readily available to mainstream designers," said Shawn McCloud, Vice President of Marketing at Calypto. “They are written entirely in SystemC and tuned through the Catapult C synthesis tool. These interfaces are a great example of the benefits of mixing cycle accurate SystemC for control with abstract SystemC/C++ to implement a hardware subsystem.”
The AXI interface library is tuned so the resulting hardware is optimized for the user’s specific performance requirements, configuration mode and target technology. Availability in April, please contact Calypto Sales for specific pricing and information.
About Calypto’s Products
Catapult High Level Synthesis, Calypto’s SLEC® (Sequential Logic Equivalence Checking) and PowerPro® platforms are used by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable electronic system level design by engineers to dramatically improve design quality and reduce power consumption of their system-on-chip (SOC) devices.
About Calypto
Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.
Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.
More information can be found at www.calypto.com.
|
Related News
- NEC Releases High Level Synthesis IDE, CyberWorkBench World's 1st Dedicated FPGA Version
- BDTI Certified Results Show PICO High Level Synthesis Platform Produces Quality of Results Comparable to Hand-coded RTL
- VaST Expands Model Library with High Performance ARM PrimeCell® Models and AXI Bus
- ARM Delivers First Transaction-level SystemC Models For System-level Verification
- GLOBALFOUNDRIES and SiFive to Deliver Next Level of High Bandwidth Memory on 12LP Platform for AI Applications
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |