Who wins when Cortex-M adds RTOS?
Richard Barry, FreeRTOS.org
EETimes (3/6/2012 12:43 PM EST)
Richard Barry of FreeRTOS.org examines who the winners and losers will be in ARM's decision to add an RTOS to its Cortex-M hardware abstraction layer, through the release of CMSIS 3 (Cortex Microcontroller Software Interface Standard 3).
A significant development was announced at Embedded World 2012 that directly affects the RTOS industry--the release of CMSIS 3.
The Cortex Microcontroller Software Interface Standard (CMSIS) is a hardware abstraction layer that provides a standard software interface to the Cortex-M core. It's equally applicable to all Cortex-M based microcontrollers, so it's microcontroller-vendor independent. CMSIS simplifies software reuse and reduces a team's learning curve on the Cortex-M by providing a library of Cortex-M core-specific interface functions and definitions. For example, it provides a function that sets the priority of an interrupt, because the interrupt controller (NVIC) is part of the Cortex-M core itself, and not a separate peripheral as it is on ARM7-based microcontollers.
E-mail This Article | Printer-Friendly Page |
Related News
- eT-Kernel Real-Time Operating System Supports ARMv8-M Architecture for Next-Generation ARM Cortex-M Family
- Who's at fault when code kills?
- Arm Extends Cortex-M Portfolio to Bring AI to the Smallest Endpoint Devices
- Green Hills Software adds support for production-ready RTOS and tools to Imagination Technologies' RISC-V CPUs
- Cartesiam Transforms Edge AI Development for Industrial IoT
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models