OCP-IP Announces Newly Enhanced Advanced Accellera Systems Initiative SystemC TLM Kit
BEVERTON, Ore.-- April 3, 2012 --Open Core Protocol International Partnership (OCP-IP) today announced the availability of version 2_2x2_2 of the OCP Modeling Kit. The new version boasts greater robustness of data in payload-event-queues, a modification of thread-busy signaling API, added support for interrupts, sideband error signaling, sideband user flags, added TLM2-native adapters between TL3 and TL1, and added TLM2-native adapters between TL1 and RTL signals (TL0).
The work by OCP-IP’s System Level Design Working Group ensures continued alignment with the Accellera Systems Initiative SystemC TLM-2 standard and is the most advanced TLM-2 based, industry-ready kit in existence today. The Kit is free as part of OCP-IP membership entitlement and saves users hundreds of thousands of dollars each year in development, documentation, and training costs by enabling them to model their bus fabric to leverage this OCP-IP SLD modeling kit.
The new revision continues to support and leverage Accellera Systems Initiative SystemC TLM-2 for all levels of abstraction and includes TL4 which is equivalent to Accellera’s "loosely-timed” (LT) level. TL1 is fully cycle-accurate, including support for clock cycle synchronization and combinatorial paths. TL2 handles intra-burst timing. TL3 and TL4: inter-burst or no timing, equivalent to Accellera’s Base Protocol.
The Kit includes everything needed for immediate use. For a detailed listing of everything included see http://www.ocpip.org/uploads/documents/OCP_TLM_Datasheet.new.pdf.
A fully functional version of the Kit without monitors is also available to non-members, via click through research license agreement from www.ocpip.org.
This Kit was developed by OCP-IP member companies working with Greensocs, Ltd. It interoperates seamlessly with other TLM utilities, such as GreenSocket from GreenSocs.
Companies interested in joining the OCP-IP System Level Design Working Group should contact admin@ocpip.org.
For the latest information on OCP-IP please see our newsletter at http://www.ocpip.org/newsletters.php
About OCP-IP
Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.OCPIP.org.
|
Related News
- OCP-IP Provides Virtual Platform Leveraging Advanced OCP SystemC TLM Modeling Kit
- OCP-IP Delivers Even More OSCI TLM 2.0 Compatibility in Advanced SystemC TLM Kit
- OCP-IP Delivers New Advanced SystemC TLM Kit
- Accellera Systems Initiative Acquires Open Core Protocol Standard and Infrastructure to Strengthen Interoperability in Electronic Standards Development
- OCP-IP Develops New Relaxed Commercial Use License for SystemC Transaction Level Modeling Kit
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |