MIPS Technologies Expands TSMC-Optimized Hard Core Offerings With Availability of the MIPS64[tm] 5Kc[tm] Core
MIPS Technologies Expands TSMC-Optimized Hard Core Offerings With Availability of the MIPS64[tm] 5Kc[tm] Core
Silicon-Tested MIPS® Cores Offer More Performance, Lower Power Consumption and Smaller Die Size Than Competitive Cores
SAN JOSE, Calif., and TAIPEI, Taiwan, Feb. 6, 2002 - MIPS Technologies, Inc., (Nasdaq: MIPS, MIPSB), a leading provider of industry-standard processor architectures and cores for digital consumer and network applications, and Taiwan Semiconductor Manufacturing Company Ltd. (NYSE: TSM), the world's largest dedicated semiconductor foundry, announced the availability of the MIPS64[tm] 5Kc[tm] hard core. The new 64-bit hard core is in addition to the line of 32-bit hard cores already offered by MIPS Technologies for manufacture at TSMC. Compared to other foundry hard cores, MIPS® hard cores offer unparalleled performance for end systems needing higher throughput, lower power consumption and smaller die size in a cost-effective 0.18 micron industry-standard process.
This announcement coincides with the opening of MIPS Technologies' new sales and marketing office in Taiwan. The event, held in Taipei, was attended by senior executives of MIPS Technologies, TSMC and an array of Taiwan government representatives and executives from new regional partners and distributors (see companion announcement).
MIPS hard cores enable today's semiconductor companies to use a cost-effective industry-standard foundry process with minimum integration cost and reduced risk to deliver robust, high-performance SOC designs that create higher system value for their customers. Semiconductor manufacturers and system OEMs trying to meet the demands of high-growth markets such as consumer electronics and communications require high-performance, low-power processors for feature-rich products, and also face enormous competitive pressures to shorten product design cycles and minimize development cost. A MIPS foundry hard core, which can be dropped into an SOC or ASIC design, allows them to get to market faster, lower development costs and reduce risk.
Compared to other foundry hard cores, MIPS hard cores offer unparalleled performance for creating cost-effective systems that need higher throughput, lower power consumption and smaller die size. For example, the 5Kc hard core in a 0.18-micron process offers 25 percent more performance than its nearest competitor in a more costly 0.15-micron process. Other available MIPS hard cores include the MIPS32 4Kc[tm] and 4Km[tm] cores; all are currently ported to TSMC's 0.18 micron core CMOS logic process. The 4Kc hard core delivers 18 percent more performance than its nearest competitor in a 60-percent smaller die area, resulting in lower silicon cost. Leveraging the higher performance of the 4Kc core results in 25 percent lower power consumption.
"At process geometries of 0.18 micron and below, the historical tradeoff of size versus performance changes dramatically, making these 64-bit processor cores very attractive for a range of SOC applications," said Genda Hu, vice president of marketing at TSMC. "The MIPS64 5Kc core's high-performance attributes, added to the compact MIPS32 4K family of hard cores, are a superb combination of software-compatible, ready-to-use cores for SOC development."
"These foundry hard cores offer tremendous value with the most competitive performance metrics in the SOC market today," said Kevin Meyer, vice president of marketing at MIPS Technologies. "In the current economic climate, competitive companies are driven to develop feature-rich products on high performance and scalable platforms. Now, those companies can do so using industry standard processor cores that enable higher-value products and, therefore, higher profit margins."
SOC designer who have used 32-bit cores from MIPS competitors, can now take advantage of The MIPS64 5Kc, with its 64-bit technology, without paying a penalty in die size or power consumption. Features of the 5Kc hard core include:
- A full 64-bit, 6-stage pipeline.
- 64K instruction cache, 64K data cache.
- A 32 dual-entry TLB memory management unit.
- A fast multiply/divide unit with single-cycle MAC instructions.
- 32 64-bit general-purpose registers.
- Gated clocks for reduced power consumption.
- Using the TSMC 0.18-micron CL018G process, the die size of the 5Kc, including caches, is less than 20 mm2.
- Power consumption is less than 3.1 mW/MHz and typical speed(1) is 310MHz, delivering 435 DMIPS performance.
- A full 32-bit, 5-stage pipeline.
- 16K instruction cache, 16K data cache.
- A 16 dual-entry TLB memory management unit.
- A fast multiply/divide unit with single-cycle MAC instructions.
- 32 general-purpose registers.
- Gated clocks for reduced power consumption.
- Using TSMC's 0.18-micron CL018G process, the die size of the 4Kc, including the caches, is less than 7 mm2.
- Power consumption is less than 2 mW/MHz and typical speed(1) is 263MHz, delivering 342 DMIPS performance.
- A full 32-bit, 5-stage pipeline.
- 8K instruction cache, 8K data cache.
- A fixed address translation memory management unit.
- A fast multiply/divide unit with single-cycle MAC instructions.
- 32 general-purpose registers.
- Gated clocks for reduced power consumption.
- Using the TSMC 0.18-micron CL018G process, the die size of the 4Km, including caches, is less than 4.7 mm2.
- Power consumption is less than 1.7 mW/MHz and typical speed(1) is 263MHz, delivering 342 DMIPS performance.
(1) Typical speed condition: TT process corner, 25°C Tj, Norminal Vdd without clock uncertainty
Pricing and Availability
These TSMC-optimized foundry 32- and 64-bit hard cores are available for licensing today from MIPS Technologies for license fees as low as $250,000.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and network applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.
# # #
MIPS® is a registered trademark in the United States and other countries, and MIPS-based[tm], MIPS32[tm], 4Kc[tm], 4Km[tm], MIPS64[tm] and 5Kc[tm] are trademarks of MIPS Technologies, Inc. All other trademarks referred to herein are the property of their respective owners.
Related News
- MIPS Technologies' 32-Bit TSMC-optimized cores available
- MIPS Technologies Licenses MIPS64[tm] 5Kf[tm] and MIPS32[tm]4KEc[tm] Processor Cores to LSI Logic
- MIPS Technologies and IN2FAB Technology Team to Deliver Optimized Solutions for MIPS-based[tm] SOC Design
- MIPS Technologies, Intrinsix Alliance Offers SoC Design Services for MIPS-Based[tm] Solutions
- MIPS Technologies Partners with Synopsys to Provide DesignWare Users Easy Access to MIPS-Based[tm] SoC Design Environment
Breaking News
- Tenstorrent Expands Deployment of Arteris' Network-on-Chip IP to Next-Generation of Chiplet-Based AI Solutions
- Siemens' Tessent In-System Test software enables advanced, deterministic testing throughout the silicon lifecycle
- EnSilica plc - Audited Full Year Results for the Year Ended 31 May 2024
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
Most Popular
- Arm's power play will backfire
- Siemens strengthens leadership in industrial software and AI with acquisition of Altair Engineering
- Sondrel announces CEO transition to lead next phase of growth
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
E-mail This Article | Printer-Friendly Page |