TSMC to offer SoC design-to-manufacturing service

TSMC will offer the service in the third quarter for production at the 90-nanometer node on 200-mm wafers, and then on 300-mm wafers in the first quarter of 2003. Hu said Nexsys will better coordinate TSMC's "family of processes" offered in logic and mixed-signal areas to provide an easier design and manufacturing interface for engineers.

TSMC announced Nexsys Thursday (April 11) at a TSMC technology forum here. During the sessions, Hu and other TSMC executives stressed the need for greater integration between design and manufacturing services as the industry follows the SoC trend. TSMC is rolling out the package to address this front-end need and also said it would increase its attention to testing and packaging services, by boosting its in-house capacity and increasing coordination with third-party sources.

TSMC also released details of an SoC process at the 90-nm node. It will include a triple-gate oxide option and hit a core voltage of 1.0 V, will support gate lengths of 45 to 65 nm and provide a best-case gate delay of 7.9 picoseconds. The high-performance process will also enable use of a low-k dielectric with a value of 2.9 and will allow up to 10 layers of dual-damascene copper metalization.

More 300-mm fabs

In a related announcement, TSMC deputy chief executive officer, F.C. Tseng, said the company would break ground on two more 300-mm wafer fabrication facilities i n Taiwan "later this year." One will be in the Hsinchu Science Park, the other in the southern Tainan Science Park. No other details were offered. TSMC is in pilot production at Fab 12, its 300-mm wafer facility in Hsinchu, and is installing the clean room at Fab 14, its second full-scale 300-mm wafer fab, located in Tainan.