Arteris FlexNoC Interconnect IP Licensed by Core Logic for Mobile and Multimedia Processors
Interconnect IP scales with SoC complexity; reducing routing congestion, easing timing closure and increasing performance
SUNNYVALE, California — April 17, 2012 — Arteris Inc., the inventor and leading supplier of network-on-chip (NoC) interconnect IP solutions, today announced that Core Logic has selected Arteris® FlexNoC™ interconnect IP as the backbone SoC interconnect in its next-generation mobile and multimedia processors.
Core Logic is one of Korea’s largest fabless semiconductor vendors, with expertise in low power mobile and multimedia systems-on-chip (SoCs). As the complexity of their SoCs increased, along with back-end timing and routing congestion issues, Core Logic found that its previous interconnect IP solution could not scale to meet their advancing needs.
“Arteris is the first company to offer NoC technology for bus architecture use, and after our technical evaluation we know it will help us handle our complex SoC routing and timing issues,” said Cabin Koo, Chief Engineer at Core Logic. “We are confident that Arteris FlexNoC will help us eliminate back-end issues while simultaneously shrinking our development schedules. Arteris FlexNoC interconnect IP is a must to create advanced SoCs, and we are using it for multiple design projects.”
“Core Logic’s decision to adopt Arteris FlexNoC as the backbone SoC interconnect within their most important chips is a strong vote of confidence in Arteris’ unique network-on-chip technology,” said K. Charles Janac, President and CEO of Arteris. “Arteris NoC technology allows the creation of complex SoCs while avoiding the problems of back-end wire routing congestion and timing closure issues inherent in older technologies.”
About Arteris
Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs.
Founded by networking experts and offering the first commercially available Network-on-Chip IP products, Arteris operates globally with headquarters in Sunnyvale, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.
|
Arteris Hot IP
Related News
- Actions Semiconductor Licenses Arteris FlexNoC Interconnect IP for Multimedia Application Processors
- Arteris FlexNoC Interconnect IP Licensed by Freescale for i.MX Applications Processors
- Arteris FlexNoC Interconnect Licensed by Telechips for Use in Advanced Automotive Applications
- Arteris FlexNoC Interconnect Licensed by Microchip Technology for Microcontroller Development
- Arteris IP FlexNoC Interconnect and Resilience Package Licensed in Neural Network Accelerator Chip Project Led by BMW Group
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |