nSys releases verification IP blocks using OpenVera hardware verification language

Netsys Software Pvt. Ltd. (nSys), a solution provider for emerging standards, announced the availability of two OpenVera™ verification intellectual property (IP) offerings that dramatically reduce the verification time of complex system-on-chip (SoC) designs. OpenVera verification IP cuts down verification time by providing a re-useable verification environment, including stimulus generators, protocol monitors and objects for functional coverage analysis.

"We are focused on easing time-to-market pressure on product development teams by reducing their verification time and effort," said Atul Bhatia, director at nSys. "With OpenVera verification IP, verification engineers can generate stimulus for their SoCs immediately, by instantiating our OpenVera models, saving months of effort in creating and debugging the test environment." 

nSys plans to offer a number of OpenVera verification IP solutions, starting with UART and IEEE 1284, which are commonly used on SoCs. The nSys family of OpenVera verification IP provides a consistent interface for integrating into an SoC verification environment, making it easy for engineers to use multiple OpenVera verification IP solutions in a verification environment.

"nSys is a charter member of the OpenVera Catalyst Program making important contributions to the PC and server markets," said Jim Watts, OpenVera program manager at Synopsys, Inc. (Nasdaq:SNPS) "A goal of Synopsys' OpenVera Catalyst Program is to accelerate the availability and proliferation of OpenVera verification IP solutions to enhance verification productivity for our mutual customers.This goal is achieved by active participation

The OpenVera verification IP solutions from nSys offer a rich set of features, including:

 
Full support of automatic random (including constrained random) and directed testing (including error generation/injection).
Built-in checking mechanism with on-the-fly protocol checking.
Built-in monitors. 
Extensive support for functional coverage such as: closed loop testing, cross-coverage based on all the variable parameters and accumulated coverage across multiple simulation runs.
Scalable architecture for use as standalone test environment or embedding in an SoC environment.
Programmable message logging capabilities such as ERROR/WARNING/INFO/DEBUG.
Flexibility for stopping tests based upon packet count, error/warning count, and time.
Object-oriented architecture to support plug and play use model.
Support for Verilog as well as VHDL implementations.