RF Engines uses its signal processing expertise to implement one of the world’s fastest FFT cores

The vectis4000R2 core can continuously process data at a sample rate of up to 200 MSPS (Megasamples Per Second), which the company believes is one of the world's fastest FFT cores of its type. Not only is the vectis family designed for high performance, but it is also designed to be optimised for minimal silicon use with this complex 4096-point version fitting in a single 1M gate Xilinx Virtex/E FPGA. The cores are fully pipelined for maximum data throughput and complement RFEL's existing range of Pipelined Frequency Transform™ (PFT) products.

These IP cores are available for licence in net list or bit stream form and are intended for use in applications where processing speed is critical and optimum use of available silicon is required such as in high speed networking subsystems, VDSL communication systems and defence applications including electronic warfare, radar and signals intelligence systems design.

"One of the most important points is that we have a fully implemented design working in silicon, rather than just vapourware. We have used our expertise in providing high performance solutions for projects requiring complex front end, real time, wide and narrow band, flexible signal channelisation to create this ultra fast FFT core design," explained John Lillington, RFEL's CTO. "The design uses a high degree of parallelism; the multipliers used are optimised for the target device allowing flexibility to use a mixture of embedded and logic built multipliers. This flexibility is extremely important when trading off power, speed and adding other processing around the core on the same device. We confidently expect to further refine further the upcoming cores in this family, achieving significantly faster performances (>800MHz) with higher radix architectures in VirtexII devices."

The first product in the vectis range is the vectis4000R2 - a Radix 2 DIF (Decimate In Frequency) Pipelined FFT that is optimised for Xilinx Virtex/E. Significant performance increases are expected when implemented in VirtexII devices. The FFT core is suitable for implementation in other high performance FPGAs that have sufficient internal RAM to support the designs, such as the Altera Stratix announced recently. A downloadable whitepaper, which provides a more detailed specification, is available on the web on www.rfel.com

The whole 4096-point FFT design fits into a single Xilinx Virtex1000E-ehq240, using 8478 slices (68% of the logic resource), and 58 out of the 96 block RAM available (thus leaving space for other processing.). An optional bit reverser uses 32 block RAMs and a small amount of additional logic resource.
 

Additional information

As the FFT core is an optimised pipelined architecture, unlike resource sharing single butterfly architectures, its physical size is dependent on the size of FFT to be performed. Therefore the delivered core is of a set size as it is programmed with that specific n-point FFT configuration. It may be possible to provide a core for say a 4096-point transform that can also select smaller transforms (e.g. 512, 256, 128, etc). This provides better flexibility of operation but would not be an optimum use of silicon.

The vectis4000R2 core is delivered as an edif or ngo netlist with .ucf user constraints file. Alternatively, it can be supplied as a bit stream if the FFT target device is fully defined and only holds the FFT core. VHDL test benches are provided along with a VHDL simulation model. Supporting documentation including data sheets and user guides are included. Design support services for implementing the core into the target design, as well as debugging support, are available if required.

The throughput rate of this pipelined core is around 8 times faster than the typical recycling architecture cores. This higher throughput allows continuous processing without any of the input data being lost.

Availability and Cost

The vectis4000R2 core is available for immediate licensing. Other variants of the core in terms of FFT length, input data width, bit growth per stage, twiddle width and blockRAM / distributed memory split can be supplied under contract. RFEL can optimise the core based on exact customer requirements.

The bit width (word length) of the data or twiddles is not fixed and, depending on the system requirements, can be tailored throughout the stages of the FFT to maintain the required dynamic range. Bit width is a factor that affects silicon area, so should be given appropriate consideration.

Accuracy and Precision are system design considerations that affect data bit width and twiddle width. RFEL can offer system engineering advice to aid the selection of the optimal core configuration.

The core is supplied under an Application Licence with pricing based on an up front payment and royalty per use.

About RF Engines Limited

RFEL is a UK based designer of high specification signal processing cores, sold as intellectual property (IP) for inclusion in SoC and semiconductor devices for applications in the defence, communications and instrumentation markets. More specifically it is a solutions provider for projects requiring complex front end, real time, wide and narrow band, flexible channelisation. RFEL provides a range of standard cores covering multiple FFT and unique PFT techniques, as well as design services for specialist applications. RFEL is located at Innovation Centre, St Cross Business Park, Newport PO30 5WB, Isle of Wight, United Kingdom.

Further information on RFEL can be found at www.rfel.com, phoning on +44 (0) 1983 550326 or e-mail : info@rfel.com.