ICScape Grows Globally
Design Closure Startup with Over 100 Tapeouts Gets $28 million in Funding
Santa Clara, California – May 14, 2012 – ICScape Inc. today announced that after enabling over 100 successful customer tapeouts, it is now ready to market its solutions worldwide. The expansion is driven by US$28 million in financial backing the company received in 2011, mostly from China Electronics Corporation (CEC), China’s largest electronics conglomerate with 2011 revenue of over US$23 billion.
ICScape was founded in 2005 by Steve Yang and Jason Xing who, formerly, as members of the technical staff at Sun Microsystems and major EDA companies, addressed design closure issues in complex SOCs. Initial funding and guidance was provided by David Tsang, co-founder and managing partner of Acorn Campus Ventures. Tsang, who was also the founder and former CEO of Oak Technology, remains an advisor to the company.
The US$28 million funding was provided to the merged entity of ICScape and CEC subsidiary, Huada Empyrean Software (HES) Company, Ltd. Together, they were spun out into one organization that combines the silicon-proven SOC design closure products from ICScape and production-proven analog/mixed signal products from one of the largest design companies in CEC’s portfolio. Weiping Liu (CEO of HES) is the CEO of the merged operation while ICScape’s founding team manages all engineering operations. ICScape is also responsible for marketing all products in its portfolio around the world, outside of PRC (People’s Republic of China).
Yang, co-founder and president of ICScape said that, “based on the collective complex IC design experience of our founding team, we developed key technologies that address specific problems in design closure, and worked with strategic customers for a few years to productize those technologies. This has given us an unprecedented edge of a solid portfolio of valuable products and over 100 tapeouts as we are ready to expand worldwide.”
Executive team
Weiping Liu, CEO and Chairman, was CEO of CEC subsidiary Huada Electronic Design Co. Ltd (HED), a major fabless IC design house in China, from 2002-2009. HED went public on the Hong Kong Stock Exchange in 2009. Liu founded HES in 2009. Liu received his MSEE/BSEE from Fudan University and has over 20 years experience in EDA and IC design.
Steve Yang, Co-founder and President, started his career at Sun Microsystems as a Member of the Technical Staff, responsible for in-house CAD tool development and later became a circuit designer on one of the microprocessor design teams in the microprocessor division. Afterward, Yang joined Synopsys and was responsible for clock tree synthesis research and development in the Physical Implementation Group. Yang received his BSEE from Tsinghua University (Beijing) and Ph.D. from the University of California, San Diego.
Jason Xing, Co-founder and Vice President of Engineering, has over 15 years EDA research and development experience. In 1997, Xing joined Sun Labs after receiving his Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign. At Sun Labs, Xing did research on physical and logical concurrent design methodologies and shape-based routing algorithms. In 2001, Xing joined the internal CAD development team in the microprocessor division. Xing holds a Ph.D. from the University of Louisiana in Mathematics.
K.C. Chen, Vice President of R&D, previously was Co-founder, CTO and Sr. Vice President of R&D at Verplex Systems Inc., which was the industry leader in formal verification tools before being acquired by Cadence Design Systems in 2003. Before starting Verplex Systems in 1997, Chen held various engineering and management positions at Fujitsu Labs. Chen is also a General Partner of the NACSE Angel Fund, which he co-founded in 2004 with other successful entrepreneurs in Silicon Valley. Chen holds a Ph.D. and M.S. in Computer Science from the University of Illinois at Urbana-Champaign and has over 20 years experience in the EDA and software industries.
About ICScape
ICScape Inc. (Santa Clara, California) develops and globally markets EDA (electronic design automation) solutions that accelerate design closure and address analog/mixed signal design. Its tools have already been used successfully for design closure in the storage, wireless, base band, data communications, multimedia, graphics, chipset and power management design markets. The company is financially backed by CEC, China’s largest electronics product design conglomerate. For more information, contact ICScape at 408-727-6330. Website: www.ICScape.com
|
Related News
- Urgent Orders Boost Wafer Foundry Utilization in Q2; Global Top 10 Foundry Revenue Grows 9.6% while VIS Climbs Two Spots, Says TrendForce
- Siemens brings formal methods to high-level verification with C++ coverage closure and property checking
- Intrinsic ID Protects 500,000,000 Devices Globally: Leading the Way in Secure and Authenticated Connected Devices
- Monthly Semiconductor Sales Decrease 0.5% Globally in September
- New Cadence Certus Delivers Up to 10X Faster Concurrent Full-Chip Optimization and Signoff
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |